Datasheet
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current Controllers
______________________________________________________________________________________ 67
where V
1
is the fundamental amplitude, and V
2
through
V
6
are the amplitudes of the first five harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest
spectral component.
ADC Channel-to-Channel Crosstalk
Bias the ON channel to midscale. Apply a full-scale sine-
wave test tone to all OFF channels. Perform an FFT on
the ON channel. ADC channel-to-channel crosstalk is
expressed in dB as the amplitude of the FFT spur at the
frequency associated with the OFF channel test tone.
Intermodulation Distortion (IMD)
IMD is the total power of the intermodulation products
relative to the total input power when two tones, f
1
and
f
2
, are present at the inputs. The intermodulation prod-
ucts are (f
1
±f
2
), (2 x f
1
), (2 x f
2
), (2 x f
1
±f
2
), (2 x f
2
±
f
1
). The individual input tone levels are at -7dBFS.
Small-Signal Bandwidth
A small -20dBFS analog input signal is applied to an
ADC in such a way that the signal’s slew rate does not
limit the ADC’s performance. The input frequency is
then swept up to the point where the amplitude of the
digitized conversion result has decreased by -3dB.
Note that the track/hold (T/H) performance is usually
the limiting factor for the small-signal input bandwidth.
Full-Power Bandwidth
A large -0.5dBFS analog input signal is applied to an
ADC and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as full-
power input bandwidth frequency.
DAC Digital Feedthrough
DAC digital feedthrough is the amount of noise that
appears on the DAC output when the DAC digital con-
trol lines are toggled.
ADC Power-Supply Rejection
Power-supply rejection is defined as the shift in offset
error when the power supply is moved from the minimum
operating voltage to the maximum operating voltage.
DAC Power-Supply Rejection
DAC PSR is the amount of change in the converter’s
value at full scale as the power-supply voltage
changes from its nominal value. PSR assumes the
converter’s linearity is unaffected by changes in the
power-supply voltage.
THD x
VVVVV
V
log
=
++++
20
2
2
3
2
4
2
5
2
6
2
1
TOP VIEW
MAX11014
MAX11015
TQFN
7mm x 7mm X 0.8mm
+
13
14
15
16
17
18
19
20
21
22
23
24
ACLAMP2
GATE2
GATEV
SS
N.C.
ACLAMP1
GATE1
FILT1
FILT2
FILT3
FILT4
PGAOUT1
PGAOUT2
48
47
46
45
44
43
42
41
40
39
38
37
1
2
345678910
11
12
SCLK/SCL
N.C./A2
SPI/I2C
CS/A0
ALARM
CNVST
DGND
DV
DD
BUSY
OPSAFE2
OPSAFE1
N.C.
AGND
AV
DD
REFADC
REFDAC
DXP2
DXN2
DXP1
DXN1
ADCIN2
ADCIN1
DOUT/A1
DIN/SDA
36
35
34 33 32 31 30 29 28 27
26
25
AGND
AV
DD
AV
SS
N.C.
N.C.
RCS2+
RCS2-
RCS1-
RCS1+
N.C.
N.C.
N.C.
Pin Configuration
Chip Information
PROCESS: BiCMOS