Datasheet

MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current Controllers
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The KLUT data is stored in straight binary format.
Figure 30 details a channel 1 KLUT example with nine
entries, a range of 0.5V to 1.7V, and a step size of 256.
Assuming V
REFDAC
= +2.5V, the base value (819d) is
determined by the following equation:
Internally Timed Acquisitions
and Conversions
Clock Mode 00
In clock mode 00, power-up, acquisition, conversion,
and power-down are all initiated by writing to the ADC
conversion register and performed automatically using
the internal oscillator. This is the default clock mode.
With ADCMON set to 1, the ADC sets the BUSY output
high, powers up, scans all requested channels, stores
the results in the FIFO, and then powers down. After the
scan is complete, the BUSY output is pulled low and
the results are available in the FIFO.
05
25
4096 819
.
.
V
V
xd=
KLUT2CNFG 0xC3
KLUT1CNFG = 0 0100 1xxx 1000
0xC2
TLUT2CNFG 0xC1
T LUT1CNFG 0xC0
0x60
KLUT1 VALUE 1
KLUT1 VALUE 0
0x61
KLUT1 VALUE 3
KLUT1 VALUE 2
KLUT1 VALUE 5
KLUT1 VALUE 4
KLUT1 VALUE 7
KLUT1 VALUE 6
KLUT1 VALUE 8
0x62
0x63
0x64
0x65
0x66
0x67
0x68
KLUT1BASE = 0.4999V
KLUT2BASE 0xC7
KLUT1BASE = 0011 0011 0011 (819d)
0xC6
TLUT2BASE 0xC5
TLUT1BASE 0xC4
0.6561V
0.8124V
0.9686V
1.1249V
1.2811V
1.4374V
1.5936V
1.7499V
KLUT1 VALUE 9 = UNUSED
Figure 30. KLUT Example