Datasheet

MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current Controllers
6 _______________________________________________________________________________________
SPI-INTERFACE TIMING CHARACTERISTICS
(Note 9) (See Figure 1.)
I
2
C-INTERFACE SLOW-/FAST-MODE TIMING CHARACTERISTICS
(Note 9) (See Figure 2.)
PARAMETER
SYMBOL
CONDITIONS MIN TYP MAX UNITS
SCLK Clock Period t
CP
40 ns
SCLK High Time t
CH
16 ns
SCLK Low Time t
CL
16 ns
DIN to SCLK Rise Setup Time
t
DS
10 ns
DIN to SCLK Rise Hold Time t
DH
0ns
SCLK Fall to DOUT Transition
t
DO
C
L
= 30pF 20 ns
CS Fall to DOUT Enable t
DV
C
L
= 30pF (Note 3) 40 ns
CS Rise to DOUT Disable t
TR
C
L
= 30pF (Note 10) 40 ns
CS Rise or Fall to SCLK Rise t
CSS
10 ns
CS Pulse-Width High t
CSW
(Note 3) 40 ns
Last SCLK Rise to CS Rise t
CSH
(Note 3) 0 ns
PARAMETER
SYMBOL
CONDITIONS MIN
TYP MAX
UNITS
SCL Clock Frequency f
SCL
0
400
kHz
Bus Free Time Between a STOP
and START Condition
t
BUF
1.3 µs
Hold Time (Repeated) for START
Condition
t
HD
;
STA
After this period, the first clock
pulse is generated
0.6 µs
Setup Time for a Repeated START
Condition
t
SU
;
STA
0.6 µs
SCL Pulse-Width Low t
LOW
1.3 µs
SCL Pulse-Width High t
HIGH
0.6 µs
Data Setup Time
t
SU
;
DAT
100 ns
Data Hold Time
t
HD
;
DAT
(Note 11) 0 0.9 µs
SDA, SCL Rise Time, Receiving t
R
(Notes 3, 12) 0
300
ns
SDA, SCL Fall Time, Receiving t
F
(Notes 3, 12) 0
300
ns
SDA Fall Time, Transmitting t
F
(Notes 3, 12, 13)
20 + 0.1 x C
B
250
ns
Setup Time for STOP Condition
t
SU
;
STO
0.6 µs
Capacitive Load for Each Bus Line
C
B
(Notes 3, 14)
400
pF
Pulse Width of Spikes Suppressed
By the Input Filter
t
SP
(Note 15) 50 ns