Datasheet

MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current Controllers
54 ______________________________________________________________________________________
Write to the HVCAL_ bits in the PGA calibration control
register to short circuit the current-sense amplifier
inputs so that only the offset is apparent at the
PGAOUT_ output and ADC input.
BUSY Output
The BUSY output goes high for a variety of reasons.
The possible causes of BUSY pulsing high include:
• The ADC is converting, but not in continuous con-
version mode
• The internal ALU core is performing a power-up
initialization
• The internal ALU core is performing a V
DAC(CODE)
calculation
• The internal ALU core is performing another function
• The self-calibration routine is taking place
When the CONCONV bit is set in the ADC conversion
register, the BUSY output does not trigger when the
ADC is converting (for all clock modes). This prevents
the continuous ADC activity from masking other
BUSY events.
The serial interface remains available regardless of the
state of BUSY, although certain commands are not
appropriate. For example, if BUSY is high for an ADC
operation, reading the FIFO does not produce the
result for the current conversion. Also, if BUSY triggers
due to an ADC conversion, do not enter a second con-
version command until BUSY returns low, indicating the
previous conversion is complete.
See Figure 23 for a pair of BUSY timing examples. In
example 1, an externally timed ADC conversion trig-
gers the ADCBUSY bit in the flag register and forces
BUSY high. Next, a V
DAC(CODE)
calculation triggers the
ALUBUSY bit in the flag register and holds BUSY high.
In example 2, the V
DAC(CODE)
calculation is not
requested.
GATE1/2 OUTPUT
BUSY (OUTPUT)
BUSY TIMING: EXAMPLE 1
ADCBUSY
(FLAG REGISTER BIT)
ALUBUSY
(FLAG REGISTER BIT)
BUSY OUTPUT
ADCBUSY
(FLAG REGISTER BIT)
ALUBUSY
(FLAG REGISTER BIT)
BUSY TIMING: EXAMPLE 2
CNVST
CNVST
Figure 23. BUSY Timing