Datasheet

MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current Controllers
50 ______________________________________________________________________________________
FIFO
Read the oldest result in the FIFO by writing command
byte 80h and reading the next 16 bits at DOUT in SPI
mode and SDA in I
2
C mode. Bits D15–D12 (channel
tag) identify which ADC or LUT channel is being con-
verted. Bits D11–D0 contain the ADC/LUT conversion
results for that specific channel. Bit D11 is the MSB and
bit D0 is the LSB for all ADC and LUT data, with the
exception of the LUT configuration words. When read-
ing the LUT configuration registers, bit D12 is the MSB
and bit D0 is the LSB. See Table 25.
FLAG (Read)
Read from the flag register to determine the source of a
busy condition. Set the command byte to F6h to read
the flag register. Bits D15–D7 are don’t care. See Table
26. The RESTART bit, D6, is set to 1 after either a
watchdog timer reset or by commanding a software
reset through the software clear register’s FULL RESET
function. RESTART is reset to a 0 after a power-on reset
or a flag register read command. The ALUBUSY bit,
D5, is set to 1 when the ALU is performing other tasks
not covered by specific status bits elsewhere in this
register. The PGABUSY bit, D4, is set to 1 when the
ALU is performing a PGA calibration.
Table 26. FLAG (Read)
BIT NAME DATA BIT
RESET
FUNCTION
X D15–D7 X Don’t care.
RESTART D6 0
RESTART is set to 1 after either a watchdog timer reset or by commanding a
software reset through the software clear register’s FULL RESET function.
RESTART returns to 0 after a power-on reset or a flag register read command.
ALUBUSY D5 0
ALUBUSY is set to 1 when the ALU is performing other tasks not covered by
specific status bits elsewhere in this register. This includes, for example, the
internal memory initialization after power-up.
PGABUSY D4 0
PGABUSY is set to 1 when the ALU is performing a PGA calibration (whether
commanded or self-timed).
ADCBUSY D3 0
ADCBUSY is set to 1 when the ADC is busy, an ALARM value is being checked,
or the ADC results are being loaded into the FIFO. ADCBUSY returns to 0 after
the ADC completes all of the conversions in the current scan.
VGBUSY D2 1
VGBUSY is set to 1 when the ALU is performing a lookup and interpolation or
V
DAC(CODE)
calculation for either channel.
FIFOEMP D1 1
FIFOEMP is set to 1 when the FIFO is empty and contains no data. FIFOEMP is
reset to 0 if data is written into the FIFO. Writing to the software clear register with
FIFOCLR set to 1 causes the FIFO to be cleared, which then sets FIFOEMP to 1.
FIFOOVR D0 0
FIFOOVR functions in one of two modes:
1) Reading the ADC data: FIFOOVR is set to 1 if the FIFO has a data overflow.
FIFOOVR is reset to 0 by reading the flag register or by clearing the FIFO
through the software clear register. Emptying the FIFO does not clear the
FIFOOVR bit.
2) Reading the LUT data: When commanding an LUT read, the FIFO is no longer
allowed to overflow (as it is for normal ADC monitoring). FIFOOVR is set to 1 if
the LUT is full and set to 0 if the LUT is not full, for that instant in time only.