Datasheet

MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current Controllers
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Table 20. SHUT (Write)
Table 21. LDAC (Write)
BIT NAME DATA BIT
RESET STATE
FUNCTION
X D15–D12 X Don’t care.
FULLPD D11 1
Set to 1 to power down all internal blocks. FULLPD takes precedence
over any of the other power-down control bits. All commands in progress
are suspended and the DACs and ADC are disabled. The serial
interface remains functional. FULLPD is set to 1 on power-up. Set the
FULLPD bit to 0 after power-up and before writing any other commands
to activate all internal blocks.
FBGON D10 0
Set to 1 to force the internal bandgap voltage block to power up, remain
powered up between conversions, and avoid the 50µs reference power-
up delay time. Forcing the internal reference to remain on increases the
power dissipation. Set FBGON to its default state of 0 to power the
bandgap voltage as required by the ADC.
WDGPD D9 0
Set to 1 to turn off the watchdog oscillator. The watchdog oscillator
monitors the internal ALU and resets the logic state to the startup
condition after 80ms. This reduces power consumption but prevents the
self-monitoring function of the watchdog timer.
OSCPD D8 0
Set to 1 to power down the internal oscillator. OSCPD is automatically
reset to 0 after receiving the next interface command.
PD2-3 D7 1 Set to 1 to power down the channel 2 current-sense amplifier.
PD2-2 D6 1 Set to 1 to power down the channel 2 gate-drive amplifier.
PD2-1 D5 1
Set to 1 to power down the channel 2 DAC summing node
(MAX11014)/DAC buffer (MAX11015). The summing node acts as a
buffer in the MAX11015.
PD2-0 D4 1 Set to 1 to power down the channel 2 DAC.
PD1-3 D3 1 Set to 1 to power down the channel 1 current-sense amplifier.
PD1-2 D2 1 Set to 1 to power down the channel 1 gate-drive amplifier.
PD1-1 D1 1
Set to 1 to power down the channel 1 DAC summing node
(MAX11014)/DAC buffer (MAX11015). The summing node acts as a
buffer in the MAX11015.
PD1-0 D0 1 Set to 1 to power down the channel 1 DAC.
BIT NAME DATA BIT
RESET STATE
FUNCTION
X D15–D2 X Don’t care.
DACCH2 D1 N/A
Set to 1 to load the channel 2 DAC output register with the value stored
in the channel 2 DAC input register.
DACCH1 D0 N/A
Set to 1 to load the channel 1 DAC output register with the value stored
in the channel 1 DAC input register.