Datasheet

MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current Controllers
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HCFG (Read/Write)
Select each channel’s maximum GATE voltage, clock
mode, ADC monitoring, DAC and ADC reference
modes by setting bits D11–D0 in the hardware configu-
ration register. Set the command byte to 38h to write to
the hardware configuration register. Set the command
byte to B8h to read from the hardware configuration
register. Bits D15–D12 are don’t care. Set the
CH2OCM1/0 bits, D11 and D10, to determine the maxi-
mum positive GATE2 output voltage. Set the
CH1OCM1/0 bits, D9 and D8, to determine the maxi-
mum positive GATE1 output voltage. See Table 10.
Set the ADCMON bit, D6, to 1 to load the ADC results
into the FIFO. Set ADCMON to 0 to not load ADC
results into the FIFO. Set the CKSEL1/0 bits, D5 and
D4, to determine the conversion and acquisition timing
clock modes. See Table 10b. Also, see the
Internally
Timed Acquisitions and Conversions
and the Externally
Timed Acquisitions and Conversions sections. Set the
ADCREF1/0 bits, D3 and D2, to determine the ADC ref-
erence source. See Table 10c. Set the DACREF1/0 bits,
D1 and D0, to determine the DAC reference source.
See Table 10d.
SCFG (Read/Write)
Write to the software configuration register to determine
whether a V
DAC(CODE)
calculation value is loaded to
the DAC input register or DAC input and output regis-
ter. This register also sets the control modes for the K
parameter and temperature lookup values in the
V
DAC(CODE)
calculation. Set the command byte to 3Ah
to write to the software configuration register. Set the
command byte to BAh to read from the software config-
uration register.
BIT
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
D0
RESET
STATE
XXXX000000000000
BIT VALUE
XXXX
MSB——————————
LSB
BIT NAME DATA BIT
RESET STATE
FUNCTION
X D15–D12 X Don’t care.
CH2OCM1 D11 0
CH2OCM0 D10 0
Maximum GATE2 voltage control bits.
CH1OCM1 D9 0
CH1OCM0 D8 0
Maximum GATE1 voltage control bits.
X D7 X Don’t care.
ADCMON D6 0
ADC monitor bit. Set to 1 to load ADC results into the FIFO. Set to 0 to not
load any ADC results into the FIFO. The value of ADCMON does NOT
affect whether the results from any particular ADC conversion are
checked against ALARM limits or examined for changes to the
V
DAC(CODE)
equations.
CKSEL1 D5 0
CKSEL0 D4 0
Clock mode and CNVST configuration bits.
ADCREF1 D3 0
ADCREF0 D2 0
ADC reference select bits.
DACREF1 D1 0
DACREF0 D0 0
DAC reference select bits.
X = Don’t care.
Table 9. VL1 and VL2 (Read/Write)
Table 10. HCFG (Read/Write)