Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsLinear ICsMAX11014BGTM+

MAX11014/MAX11015

Automatic RF MESFET Amplifier

Drain-Current Controllers

32 ______________________________________________________________________________________

The MAX11014/MAX11015 communicate between the

internal registers and external bus lines through the serial

interface. Table 1 details the command bits (C7–C0) and

the data bits (D15–D0) of the serial input word. Table 2

details the command byte and the subsequent register

accessed. Tables 3–27 detail the various read and write

internal registers and their power-on reset states.

On power-up, the MAX11014/MAX11015 are in full

power-down mode (see the

SHUT (Write)

section). To

HEX CODE

WRITE READ

ADC Conversion ADCCON 62 —

ALARM Flag Register ALMFLAG — F8

Channel 1 DAC Input IPDAC1 48 —

Channel 1 DAC Input and Output THRUDAC1 4A —

Channel 1 High GATE Voltage ALARM Threshold VH1 28 A8

Channel 1 High Sense Voltage ALARM Threshold IH1 24 A4

Channel 1 High Temperature ALARM Threshold TH1 20 A0

Channel 1 K Parameter USRK1 44 —

Channel 1 Low GATE Voltage ALARM Threshold VL1 2A AA

Channel 1 Low Sense Voltage ALARM Threshold IL1 26 A6

Channel 1 Low Temperature ALARM Threshold TL1 22 A2

Channel 1 V

SET

VSET1 40 —

Channel 2 DAC Input IPDAC2 4C —

Channel 2 DAC Input and Output THRUDAC2 4E —

Channel 2 High GATE Voltage ALARM Threshold VH2 34 B4

Channel 2 High Sense Voltage ALARM Threshold IH2 30 B0

Channel 2 High Temperature ALARM Threshold TH2 2C AC

Channel 2 K Parameter USRK2 46 —

Channel 2 Low GATE Voltage ALARM Threshold VL2 36 B6

Channel 2 Low Sense Voltage ALARM Threshold IL2 32 B2

Channel 2 Low Temperature ALARM Threshold TL2 2E AE

Channel 2 V

SET

VSET2 42 —

First-In First-Out Memory FIFO — 80

Flag Register FLAG — F6

Hardware ALARM Configuration ALMHCFG 3C BC

Hardware Configuration HCFG 38 B8

LUT Address LUTADD 7A —

LUT Data LUTDAT 7C FC

PGA Calibration Control PGACAL 5E —

Shutdown SHUT 64 —

Software ALARM Configuration ALMSCFG 3E BE

Software Clear SCLR 74 —

Software Configuration SCFG 3A BA

Software Load DAC LDAC 66 —

Table 2. Register Listing (see

Appendix: Startup Code Example

for sample startup

sequence)