Datasheet
MAX11014/MAX11015
Automatic RF MESFET Amplifier
Drain-Current Controllers
______________________________________________________________________________________ 21
Connect the MESFET drain to the RCS_- input. Connect
the MESFET’s gate to the GATE_ output. Set the GATE_
voltage to -2 x V
REFDAC
to turn the MESFET fully off.
Set the GATE_ voltage to 0V to turn the MESFET fully
on. See Figure 7.
The MAX11014/MAX11015 GATE_ output voltage can
be clamped to the external voltage applied at
ACLAMP_. Setting OPSAFE_ high clamps the GATE_
voltage unconditionally. The GATE_ can also be
clamped by different commands issued through the
serial interface. These devices can also monitor the
alarms through the software to modify the clamping
mechanism. See the
Automatic GATE Clamping
and
ALMHCFG (Read/Write)
sections.
12-Bit ADC Description
The MAX11014/MAX11015 ADCs use a fully differential
successive-approximation register (SAR) conversion
technique and on-chip track-and-hold (T/H) circuitry to
convert temperature and voltage signals into 12-bit dig-
ital results. The analog inputs accept single-ended
input signals. Single-ended signals are converted using
a unipolar transfer function. See the
ADC Transfer
Function
section for more details.
The internal ADC block converts the results of the inter-
nal die temperature, remote diode temperature read-
ings, current-sense voltages, and ADCIN_ voltages.
The ADC block also reads back the GATE_ analog out-
put voltage and converts it to a 12-bit digital result. The
conversion results are written to the FIFO memory. The
FIFO holds up to 15 words (each word of 16 bits) with a
leading 4-bit channel tag to indicate which channel the
12-bit data comes from. See Table 25. The FIFO reads
back data words either one at a time or continuously.
See the
ADCCON (Write)
section. The FIFO always
stores the most recent conversion results and allows
the oldest data to be overwritten. The FIFO indicates an
overflow condition and underflow condition (read of an
empty FIFO) through the flag register. See the
FLAG
(Read)
section.
Analog Input Track and Hold
The equivalent circuit of Figure 8 details the
MAX11014/MAX11015’s ADCIN_ input architecture. In
track mode, a positive input capacitor is connected to
ADCIN1/ADCIN2. A negative input capacitor is con-
nected to AGND. After the T/H enters hold mode, the
difference between the sampled input voltages and
AGND is converted. The input-capacitance charging
rate determines the time required for the T/H to acquire
an input signal. The required acquisition time lengthens
with the increase of the input signal’s source imped-
ance. Any source impedance below 300Ω does not
significantly affect the ADC’s AC performance. A high-
impedance source can be accommodated either by
placing a 1µF capacitor between ADCIN_ and AGND.
The combination of the analog-input source impedance
and the capacitance at the analog input creates an RC
MESFET
FULLY
ON
OFF
GATE
VOLTAGE
GATE VOLTAGE
ALARM
THRESHOLDS
ADC CODE
READ
FROM
THE FIFO
0V
-2 x V
REFDAC
FFFh
000h
DEFAULT
V
H
= FFFh
DEFAULT
V
L
= 000h
V
GATE
WITHIN
THRESHOLDS
TOO HIGH
TOO LOW
NEW HIGH GATE
VOLTAGE ALARM
THRESHOLD
NEW LOW GATE
VOLTAGE ALARM
THRESHOLD
USER
ENTERED
DAC CODE
FFFh
000h
RCS_+ TO
RCS_- SENSE
VOLTAGE
PGAOUT
VOLTAGE
0mV
V
REFDAC
/
4
0V
V
REFADC
Figure 7. DAC Code Range