Datasheet

MAX1070/MAX1071
power-down mode. Then repeat the same sequence to
enter full power-down mode (see Figure 7). Drive CNVST
low, and allow at least 14 SCLK cycles to elapse before
driving CNVST high to exit full power-down mode. In par-
tial/full power-down mode, maintain a logic low or a logic
high on SCLK to minimize power consumption.
Transfer Function
Figure 8 shows the unipolar transfer function for the
MAX1070. Figure 9 shows the bipolar transfer function for
the MAX1071. The MAX1070 output is straight binary,
while the MAX1071 output is two’s complement.
1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
10 ______________________________________________________________________________________
DOUT
MODE
SCLK
CNVST
DOUT GOES HIGH IMPEDANCE ONCE CNVST GOES HIGH
CNVST MUST GO HIGH AFTER THE 3RD BUT BEFORE THE 14TH SCLK RISING EDGE
ONE 8-BIT TRANSFER
1ST SCLK RISING EDGE
PPD
0 0 0 D9D8 D7D6D5
NORMAL
Figure 6. SPI Interface—Partial Power-Down Mode
Figure 5. Interface-Timing Sequence
Figure 7. SPI Interface—Full Power-Down Mode
t
ACQUIRE
CONTINUOUS-CONVERSION
SELECTION WINDOW
CNVST
t
SETUP
DOUT
SCLK
41412 83 16
HIGH IMPEDANCE
S1D2D4 D3D7 D6 D5D9 D8
POWER-MODE SELECTION WINDOW
S0D0D1
1ST SCLK RISING EDGE 1ST SCLK RISING EDGE
0 0 0 D9D8 D7D6D5
DOUT
MODE
SCLK
CNVST
000000
0
FPDRECOVERYPPDNORMAL
0
DOUT ENTERS TRI-STATE ONCE CNVST GOES HIGH
EXECUTE PARTIAL POWER-DOWN TWICE
FIRST 8-BIT TRANSFER
SECOND 8-BIT TRANSFER