Datasheet
MAX1036–MAX1039
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel 2-Wire Serial 8-Bit ADCs
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 2.7V to 3.6V (MAX1037/MAX1039), V
DD
= 4.5V to 5.5V (MAX1036/MAX1038). External reference, V
REF
= 2.048V
(MAX1037/MAX1039), V
REF
= 4.096V (MAX1036/MAX1038). External clock, f
SCL
= 1.7MHz, T
A
= T
MIN
to T
MAX
, unless otherwise
noted. Typical values are at T
A
= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Setup Time for a Repeated START
Condition (Sr)
t
SU
,
STA
160 ns
Data Hold Time t
HD
,
DAT
(Note 12) 0 150 ns
Data Setup Time t
SU
,
DAT
10 ns
Rise Time of SCL Signal
(Current Source Enabled)
t
RCL
(Note 13) 20 80 ns
Rise Time of SCL Signal After
Acknowledge Bit
t
RCL1
(Note 13) 20 160 ns
Fall Time of SCL Signal t
FCL
(Note 13) 20 80 ns
Rise Time of SDA Signal t
RDA
(Note 13) 20 160 ns
Fall Time of SDA Signal t
FDA
(Note 13) 20 160 ns
Setup Time for STOP Condition t
SU
,
STO
160 ns
Capacitive Load for Each Bus Line C
B
400 pF
Pulse Width of Spike Suppressed t
SP
010ns
Note 1: The MAX1036/MAX1038 are tested at V
DD
= 5V and the MAX1037/MAX1039 are tested at V
DD
= 3V. All devices are config-
ured for unipolar, single-ended inputs.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 3: Offset nulled.
Note 4: Ground on channel; sine wave applied to all off channels.
Note 5: Conversion time is defined as the number of clock cycles (8) multiplied by the clock period. Conversion time does not
include acquisition time. SCL is the conversion clock in the external clock mode.
Note 6: The absolute voltage range for the analog inputs (AIN0–AIN11) is from GND to V
DD
.
Note 7: When AIN_/REF is configured to be an internal reference (SEL[2:1] = 11), decouple AIN_/REF to GND with a 0.01µF capacitor.
Note 8: The switch connecting the reference buffer to AIN_/REF has a typical on-resistance of 675Ω.
Note 9: ADC performance is limited by the converter’s noise floor, typically 1.4mV
P-P
.
Note 10: Electrical characteristics are guaranteed from V
DD(min)
to V
DD(max)
. For operation beyond this range, see the
Typical
Operating Characteristics
.
Note 11: Power-supply rejection ratio is measured as:
, for the MAX1037/MAX1039 where N is the number of bits and V
REF
= 2.048V.
Power-supply rejection ratio is measured as:
, for the MAX1036/MAX1038 where N is the number of bits and V
REF
= 4.096V.
Note 12: A master device must provide a data hold time for SDA (referred to V
IL
of SCL) in order to bridge the undefined region of
SCL’s falling edge (Figure 1).
Note 13: C
B
= total capacitance of one bus line in pF. t
R
, t
FDA
, and t
F
measured between 0.3V
DD
and 0.7V
DD
. The minimum value is
specified at +25°C with C
B
= 400pF.
Note 14: f
SCLH
must meet the minimum clock low time plus the rise/fall times.
VVVV
V
VV
FS FS
N
REF
55 45
2
55 45
..
..
()
−
()
[]
×
−
VVVV
V
VV
FS FS
N
REF
33 27
2
33 27
..
..
()
−
()
[]
×
−