Datasheet

B. SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
NOTE: t
ACQ
+ t
CONV
≤ 7.6μs PER CHANNEL.
S
1
SLAVE ADDRESS A
711
R
CLOCK STRETCH
NUMBER OF BITS
P or Sr
1
8
RESULT
A
1
A. SINGLE CONVERSION WITH INTERNAL CLOCK
S
1
SLAVE ADDRESS
711
R
CLOCK STRETCH
A
NUMBER OF BITS
P OR Sr
1
8
RESULT 1
A
1
A
8
RESULT 2
A
8
RESULT N
SLAVE TO MASTER
MASTER TO SLAVE
t
CONV1
CLOCK STRETCH
t
ACQ1
t
CONV2
t
ACQ2
t
CONVN
t
ACQN
t
CONV
t
ACQ
1
1
Figure 10. Internal Clock Mode Read Cycles
SLAVE ADDRESS RESULT 1 RESULT 2 RESULT N
t
CONV1
t
ACQ1
t
CONV2
t
ACQ2
t
CONVN
t
ACQN
t
CONV
t
ACQ
NUMBER OF BITS
NUMBER OF BITS
18
A
1
S
1
A
711
R
S
1
A
711
R P OR Sr
1
8
A
1
A
8
A
8
B. SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
11
SLAVE ADDRESS P OR SrRESULT
A. SINGLE CONVERSION WITH EXTERNAL CLOCK
SLAVE TO MASTER
MASTER TO SLAVE
Figure 11. External Clock Mode Read Cycles
MAX1036–MAX1039
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel 2-Wire Serial 8-Bit ADCs
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