Datasheet

MAX1002
Low-Power, 60Msps, Dual, 6-Bit ADC
_______________________________________________________________________________________ 3
AC ELECTRICAL CHARACTERISTICS
(V
CC,
V
CCO
= +5V ±5%; T
A
= +25°C; unless otherwise noted.)
Note 1: Best straight-line linearity method.
Note 2: A typical application will AC couple the analog input to the DC bias level present at the analog inputs (typically 2.35V).
However, it is also possible to DC couple the analog input (using differential or single-ended drive) within this common-
mode input range (Figures 4, 5).
Note 3: PSSR is defined as the change in the mid-gain, full-scale range as a function of the variation in V
CC
supply voltage
(expressed in decibels).
Note 4: The current in the V
CCO
supply is a strong function of the capacitive loading on the digital outputs. To minimize supply
transients and achieve the best dynamic performance, reduce the capacitive loading effects by keeping line lengths on the
digital outputs to a minimum.
Note 5: Offset-correction compensation enabled, 0.22µF at Q and I compensation inputs (Figures 2, 3).
Note 6: t
PD
and t
SKEW
are measured from the 1.4V level of the output clock, to the 1.4V level of either the rising or falling edge of a
data bit. t
DCLK
is measured from the 50% level of the clock overdrive signal on TNK+ to the 1.4V level of D
CLK
. The capac-
itive load on the outputs is 15pF.
Gain = GND, open, V
CC
GAIN = open (mid gain),
V
IN
= 50MHz, -1dB below FS
GAIN = open (mid gain)
5.7
ENOB
M
5.6 5.85
Effective Number of Bits
Gain = open (mid gain)
Gain = V
CC
(low gain)
Q channel
I channel
dB
CONDITIONS
MHz55BWAnalog Input -0.5dB Bandwidth
Msps60f
MAX
Maximum Sample Rate
-55XTLK
Gain = V
CC
(high gain)
Crosstalk Between ADCs
LSB
-0.5 0.5
OFFInput Offset (Note 5)
-0.5 0.5
dB35.4 37SINAD
Signal-to-Noise and Distortion
Ratio
Bits
5.85ENOB
L
5.8ENOB
H
(Note 5)
dB-0.2 ±0.1 0.2AM
Amplitude Match Between
ADCs
LSB-0.5 ±0.25 0.5OMM2Offset Mismatch Between ADCs
(Note 6)
(Note 6)
ns3.6t
SKEW
Data Valid Skew
ns7.1t
PD
DCLK to Data-Propagation
Delay
degrees-2 ±0.5 2PM
UNITSMIN TYP MAXSYMBOLPARAMETER
Phase Match Between ADCs
TNK+ to DCLK (Note 6) ns5.3t
DCLK
Input to DCLK Delay
ns5.5t
AP
Aperture Delay
clock
cycle
1PDPipeline Delay
DYNAMIC PERFORMANCE (GAIN = open; external 60MHz clock (Figure 7); V
INI
, V
INIQ
= 20MHz sine; amplitude -1dB below FS;
unless otherwise noted.)
TIMING CHARACTERISTICS (data outputs: R
L
= 1MΩ, C
L
= 15pF, Figure 8)