Users Guide: Network Microcontroller Supplement User Manual

High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
55
Interrupt Enable (IE)
Slave Address Register 0 (SADDR0)
SADDR0.7–0
Bits 7–0
Slave address register 0. This register is programmed with the given or broadcast address assigned
to serial port 0.
7 6543210
SFR A8h EA ES1 ET2 ES0 ET1 EX1 ET0 EX0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
EA
Bit 7
ES1
Bit 6
ET2
Bit 5
ES0
Bit 4
ET1
Bit 3
EX1
Bit 2
ET0
Bit 1
EX0
Bit 0
Global interrupt enable. This bit controls the global masking of all interrupts except power-fail interrupt,
which is enabled by the EPFI bit (WDCON.5).
0 = Disable all interrupt sources. This bit overrides individual interrupt mask settings.
1 = Enable all individual interrupt masks. Individual interrupts occur if enabled.
Enable serial port 1 interrupt. This bit controls the masking of the serial port 1 interrupt.
0 = Disable all serial port 1 interrupts.
1 = Enable interrupt requests generated by the RI_1 (SCON1.0) or TI_1 (SCON1.1) flags.
Enable timer 2 interrupt. This bit controls the masking of the timer 2 interrupt.
0 = Disable all timer 2 interrupts.
1 = Enable interrupt requests generated by the TF2 flag (T2CON.7).
Enable serial port 0 interrupt. This bit controls the masking of the serial port 0 interrupt.
0 = Disable all serial port 0 interrupts.
1 = Enable interrupt requests generated by the RI_0 (SCON0.0) or TI_0 (SCON0.1) flags.
Enable timer 1 interrupt. This bit controls the masking of the timer 1 interrupt.
0 = Disable all timer 1 interrupts.
1 = Enable all interrupt r
equests generated by the TF1 flag (TCON.7).
Enable external interrupt 1. This bit controls the masking of external interrupt 1.
0 = Disable external interrupt 1.
1 = Enable all interrupt requests generated by the INT1 pin.
Enable timer 0 interrupt. This bit controls the masking of the timer 0 interrupt.
0 = Disable all timer 0 interrupts.
1 = Enable all interrupt r
equests generated by the TF0 flag (TCON.5).
Enable external interrupt 0. This bit controls the masking of external interrupt 0.
0 = Disable exter
nal interrupt 0.
1 = Enable all interrupt requests generated by the INT0 pin.
76543210
SFR A9h SADDR0.7 SADDR0.6 SADDR0.5 SADDR0.4 SADDR0.3 SADDR0.2 SADDR0.1 SADDR0.0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R = Unrestricted read, W = Unrestricted write, -n = Value after reset
Maxim Integrated