Users Guide: DS80C390 Supplement Manual

High-Speed Microcontroller User’s Guide: DS80C390 Supplement
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XTENDED INTERRUPT ENABLE (EIE) ....................................................................................................................... 82
MOVX EXTENDED ADDRESS REGISTER (MXAX)...................................................................................................... 82
CAN 1 MESSAGE CENTER 1 CONTROL REGISTER (C1M1C)..................................................................................... 83
CAN 1 MESSAGE CENTER 2 CONTROL REGISTER (C1M2C)..................................................................................... 86
CAN 1 MESSAGE CENTER 3 CONTROL REGISTER (C1M3C)..................................................................................... 86
CAN 1 MESSAGE CENTER 4 CONTROL REGISTER (C1M4C)..................................................................................... 86
CAN 1 MESSAGE CENTER 5 CONTROL REGISTER (C1M5C)..................................................................................... 86
B REGISTER (B) ...................................................................................................................................................... 87
CAN 1 MESSAGE CENTER 6 CONTROL REGISTER (C1M6C)..................................................................................... 87
CAN 1 MESSAGE CENTER 7 CONTROL REGISTER (C1M7C)..................................................................................... 87
CAN 1 MESSAGE CENTER 8 CONTROL REGISTER (C1M8C)..................................................................................... 87
CAN 1 MESSAGE CENTER 9 CONTROL REGISTER (C1M9C)..................................................................................... 88
CAN 1 MESSAGE CENTER 10 CONTROL REGISTER (C1M10C)................................................................................. 88
EXTENDED INTERRUPT PRIORITY (EIP) ..................................................................................................................... 88
CAN 1 MESSAGE CENTER 11 CONTROL REGISTER (C1M11C)................................................................................. 89
CAN 1 MESSAGE CENTER 12 CONTROL REGISTER (C1M12C)................................................................................. 89
CAN 1 MESSAGE CENTER 13 CONTROL REGISTER (C1M13C)................................................................................. 89
CAN 1 MESSAGE CENTER 14 CONTROL REGISTER (C1M14C)................................................................................. 90
CAN 1 MESSAGE CENTER 15 CONTROL REGISTER (C1M14C)................................................................................. 90
ADDENDUM TO SECTION 5: CPU TIMING ...........................................................................................91
SYSTEM CLOCK SELECTION............................................................................................................................. 91
CHANGING THE SYSTEM CLOCK/MACHINE CYCLE CLOCK FREQUENCY....................................................................... 92
ADDENDUM TO SECTION 6: MEMORY ACCESS ................................................................................93
EXTERNAL MEMORY INTERFACING................................................................................................................. 93
USING THE COMBINED CHIP-ENABLE SIGNALS ............................................................................................................ 94
IMPLEMENTING A BOOTLOADER USING INTERNAL SRAM ............................................................................................ 95
EXAMPLE DS80C390 MEMORY CONFIGURATION...................................................................................................... 95
ADDENDUM TO SECTION 7: POWER MANAGEMENT......................................................................100
POWER MANAGEMENT MODES ............................................................................................................................... 100
SWITCHING BETWEEN CLOCK SOURCES................................................................................................................... 100
ADDENDUM TO SECTION 8: RESET CONDITIONS ...........................................................................101
RESET SOURCES.............................................................................................................................................. 101
POWER-ON/FAIL RESET ......................................................................................................................................... 101
WATCHDOG TIMER RESET...................................................................................................................................... 101
EXTERNAL RESET .................................................................................................................................................. 102
RESET OUTPUTS .............................................................................................................................................. 102
RESET STATE .................................................................................................................................................... 102
IN-SYSTEM DISABLE MODE............................................................................................................................. 103
ADDENDUM TO SECTION 10: PARALLEL I/O...................................................................................104
PORT 1 ................................................................................................................................................................. 104
PORTS 4 AND 5...................................................................................................................................................... 104
OUTPUT FUNCTIONS........................................................................................................................................ 105
ADDENDUM TO SECTION 11: PROGRAMMABLE TIMERS ..............................................................106
DIVIDE-BY-13 OPTION ........................................................................................................................................... 110
PROGRAMMABLE CLOCK OUTPUT........................................................................................................................... 110
IRDA CLOCK OUTPUT ............................................................................................................................................ 111
ADDENDUM TO SECTION 12: SERIAL I/O..........................................................................................112
ADDENDUM TO SECTION 13: TIMED ACCESS PROTECTION.........................................................113
ADDENDUM TO SECTION 16: INSTRUCTION SET DETAILS............................................................114
16-BIT (8051 STANDARD) ADDRESSING MODE............................................................................................. 114
22-BIT PAGED ADDRESSING MODE ............................................................................................................... 114
22-BIT CONTIGUOUS ADDRESSING MODE ................................................................................................... 116