Users Guide: DS80C390 Supplement Manual
High-Speed Microcontroller User’s Guide: DS80C390 Supplement 
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SFR Register. Software must clear the respective INTRQ bit in the associated CAN 0/1 Message (1-15) 
Control Register to clear the interrupt source before leaving the interrupt routine. 
The CAN 0/1 Interrupt source is connected to a change in the CAN 0/1 Status Register. Each of the status 
bits in the CAN 0/1 Status Register represents a potential source for the interrupt. To simplify the 
application and testing of a device, these sources are broken into two groups which are further enabled by 
the ERIE and STIE bits of the CAN 0/1 Control register. This allows the non-standard errors typically 
associated with development to be grouped under the STIE enable. These include the successful receive 
RXS, successful transmit TXS, wake status WKS, and general set of error conditions reported by ER2 - 
ER0. Also note that since the RXS and TXS bit are cleared by software, if a second message is received 
or transmitted before the RXS or TXS bits are cleared and after a read of the CAN 0/1 Status Register, a 
second interrupt will be generated. The remaining error sources comprise the BSS and CECE bits in the 
CAN 0/1 Status Register. These read-only bits are separately enabled by the ERIE bit in the CAN 0/1 
Control register. A read of the CAN 0/1 Status Register is required to clear either of the two groups of 
Error interrupts. It is possible that multiple changes to the Status Register may occur before the register is 
read; in that case the Status Register will generate only one interrupt. The following figure provides a 
graphical illustration of the interrupt sources and their respective interrupt enables. 
Figure 19-10. CAN INTERRUPT LOGIC 
C
Q
D 
R
CAN 0/1 STATUS 
REGISTER READ
CAN 0/1 STATUS REGISTER
CAN 0/1
CONTROL
REGISTER
BSS
ERIE STIE
EA
INTERRUPT
PRIORITY LOGIC
INTERRUPT
VECTOR 
CxIE
UPDATE CAN 0/1
INTERRUPT
REGISTER
ETI ERI
CAN 0/1 MESSAGE 1
CONTROL REGISTER
SUCCESSFUL 
TRANSMIT
MESSAGE 
CENTER 1 
SUCCESSFUL 
RECEIVE
MESSAGE CENTER 
1 
MESSAGE CENTER 1
MESSAGE CENTER 15
INTRQ
1
EC96
 WKS
RXS
TXS
ER2 
ER1
ER0










