Manual

High-Speed Microcontroller User’s Guide
Rev: 062210 52 of 176
4.2.44 Extended Interrupt Enable (EIE)
7 6 5 4 3 2 1 0
SFR E8h — —
ERTCI
EWDI EX5
EX4
EX3 EX2
RW-0 RW-0 RW-0
RW-0
RW-0 RW-0
R = Unrestricted Read, W = Unrestricted Write, -n = Value after Reset
Bits 7, 6 Reserved. Read data will be indeterminate.
ERTCI
Bit 5
Real-Time Clock Interrupt Enable. This bit enables/disables the real-time clock
interrupt on the DS87C530. This bit will read 0 on all other devices.
0 = Disable the real-time clock interrupt.
1 = Enable interrupt requests generated by the real-time clock.
EWDI
Bit 4
Watchdog Interrupt Enable. This bit enables/disables the watchdog interrupt.
0 = Disable the watchdog interrupt.
1 = Enable interrupt requests generated by the watchdog timer.
EX5
Bit 3
External Interrupt 5 Enable. This bit enables/disables external interrupt 5.
0 = Disable external interrupt 5.
1 = Enable interrupt requests generated by the
INT5 pin.
EX4
Bit 2
External Interrupt 4 Enable. This bit enables/disables external interrupt 4.
0 = Disable external interrupt 4.
1 = Enable interrupt requests generated by the INT4 pin.
EX3
Bit 1
External Interrupt 3 Enable. This bit enables/disables external interrupt 3.
0 = Disable external interrupt 3.
1 = Enable interrupt requests generated by the
INT3 pin.
EX2
Bit 0
External Interrupt 2 Enable. This bit enables/disables external interrupt 2.
0 = Disable external interrupt 2.
1 = Enable interrupt requests generated by the INT2 pin.
4.2.45 B Register (B)
7 6 5 4 3 2 1 0
SFR F0h B.7 B.6
B.5
B.4 B.3
B.2
B.1
B.0
RW-0 RW-0 RW-0 RW-0 RW-0
RW-0
RW-0
RW-0
R = Unrestricted Read, W = Unrestricted Write, -n = Value after Reset
B.7–B.0
Bits 7–0
B Register. This register serves as a second accumulator for certain arithmetic
operations. It is functionally identical to the B register found in the 80C32.
4.2.46 Real-Time Alarm Subsecond Register (RTASS)
7 6 5 4 3 2 1 0
SFR F2h RTASS.7 RTASS.6
RTASS.5
RTASS.4 RTASS.3 RTASS.2 RTASS.1 RTASS.0
RW-* RW-* RW-* RW-* RW-* RW-* RW-* RW-*
R = Unrestricted Read, W = Unrestricted Write, -n = Value after Reset, * = See description
RTASS.7–RTASS.0
Bits 7–0
Real-Time Alarm Subsecond. These bits represent the subsecond alarm which will be
compared against the RTC Subsecond register (RTCSS
;FAh). The ability of a match
between the two registers to cause an alarm is controlled by the RTC Subsecond
Register Compare Enable bit (RTCC
.7). The contents of this register will be
indeterminate following a no-battery reset, and unchanged by all other forms of reset.