Manual

High-Speed Microcontroller User’s Guide
Rev: 062210 4 of 176
6. MEMORY ACCESS.......................................................................................................76
6.1 INTERNAL PROGRAM MEMORY.......................................................................................................76
6.2 INTERNAL DATA MEMORY ..............................................................................................................76
6.2.1 ROMSIZE Feature ............................................................................................................................... 77
6.3 PROGRAM MEMORY INTERCONNECT ..............................................................................................78
6.4 DATA MEMORY INTERCONNECT .....................................................................................................79
6.5 DATA MEMORY ACCESS ................................................................................................................81
6.5.1 64-Byte Block Move With Dual Data Pointer ....................................................................................... 82
6.5.2 64-Byte Block Move Without Dual Data Pointer .................................................................................. 83
6.6 DATA MEMORY TIMING ..................................................................................................................84
7. POWER MANAGEMENT ..............................................................................................88
7.1 POWER MANAGEMENT FEATURES..................................................................................................88
7.1.1 Early Warning Power-Fail Interrupt...................................................................................................... 88
7.1.2 Power-Fail Reset.................................................................................................................................. 89
7.1.3 Power-On Reset................................................................................................................................... 89
7.1.4 Bandgap Select.................................................................................................................................... 89
7.1.5 Watchdog Wake-Up............................................................................................................................. 91
7.1.6 Power Management Summary ............................................................................................................ 91
7.2 POWER CONSERVATION ................................................................................................................93
7.2.1 Idle Mode ............................................................................................................................................. 93
7.2.2 Stop Mode............................................................................................................................................ 93
7.2.3 Ring Oscillator Wake-Up from Stop..................................................................................................... 94
7.3 POWER MANAGEMENT MODES ......................................................................................................95
7.3.1 Power Management Mode Timing....................................................................................................... 96
7.3.2 PMM and Peripheral Functions............................................................................................................ 97
7.3.3 Switchback........................................................................................................................................... 98
7.3.4 Clock Source Selection........................................................................................................................ 99
7.3.5 Using the Ring Oscillator ................................................................................................................... 100
7.3.6 Switching Between Clock Sources .................................................................................................... 101
8. RESET CONDITIONS..................................................................................................102
8.1 RESET SOURCES ........................................................................................................................102
8.1.1 Power-On/Fail Reset.......................................................................................................................... 102
8.1.2 Watchdog Timer Reset ...................................................................................................................... 102
8.1.3 External Reset.................................................................................................................................... 103
8.2 RESET STATE..............................................................................................................................103
8.3 NO-BATTERY RESET ...................................................................................................................103
8.4 IN-SYSTEM DISABLE MODE..........................................................................................................104
9. INTERRUPTS ..............................................................................................................105
9.1 INTERRUPT OVERVIEW ................................................................................................................105
9.2 INTERRUPT SOURCES..................................................................................................................106
9.2.1 External Interrupts.............................................................................................................................. 106
9.2.2 Timer Interrupts.................................................................................................................................. 107
9.2.3 Serial Communication Interrupts........................................................................................................ 107
9.2.4 Real-Time Clock................................................................................................................................. 107
9.2.5 Power-Fail Interrupt............................................................................................................................ 107
9.3 SIMULATED INTERRUPTS .............................................................................................................108
9.4 INTERRUPT PRIORITIES................................................................................................................108
9.5 INTERRUPT ACKNOWLEDGE CYCLE ..............................................................................................108
9.6 INTERRUPT LATENCY...................................................................................................................109
9.7 INTERRUPT REGISTER CONFLICTS ...............................................................................................111
10. PARALLEL I/O ............................................................................................................112
10.1 PORT 0....................................................................................................................................112
10.1.1 General-Purpose I/O.......................................................................................................................... 112
10.1.2 Multiplexed Address/Data Bus AD0–AD7.......................................................................................... 112