Datasheet

DS87C520/DS83C520 EPROM/ROM High-Speed Microcontrollers
33 of 43
MOVX CHARACTERISTICS
VARIABLE CLOCK
PARAMETER SYMBOL
MIN MAX
UNITS STRETCH
1.5t
CLCL
-5 t
MCS
=0
Data Access ALE Pulse Width t
LHLL2
2t
CLCL
-5
ns
t
MCS
>0
0.5t
CLCL
-5 t
MCS
=0
Port 0 Address Valid to ALE Low t
AVLL2
t
CLCL
-5
ns
t
MCS
>0
0.5t
CLCL
-10 t
MCS
=0
Address Hold after ALE Low for
MOVX Write
t
LLAX2
t
CLCL
-7
ns
t
MCS
>0
2t
CLCL
-5 t
MCS
=0
RD Pulse Width t
RLRH
t
MCS
-10
ns
t
MCS
>0
2t
CLCL
-5 t
MCS
=0
WR Pulse Width t
WLWH
t
MCS
-10
ns
t
MCS
>0
2t
CLCL
-22 t
MCS
=0
RD Low to Valid Data In t
RLDV
t
MCS
-24
ns
t
MCS
>0
Data Hold After Read t
RHDX
0 ns —
t
CLCL
-5 t
MCS
=0
Data Float after Read t
RHDZ
2t
CLCL
-5
ns
t
MCS
>0
2.5t
CLCL
-31 t
MCS
=0
ALE Low to Valid Data In t
LLDV
t
MCS
+t
CLCL
-26
ns
t
MCS
>0
3t
CLCL
-29 t
MCS
=0
Port 0 Address to Valid Data In t
AVDV1
t
MCS
+2t
CLCL
-
29
ns
t
MCS
>0
3.5t
CLCL
-37 t
MCS
=0
Port 2 Address to Valid Data In t
AVDV2
t
MCS
+2.5t
CLCL
-
37
ns
t
MCS
>0
0.5t
CLCL
-10 0.5t
CLCL
+5 t
MCS
=0
ALE Low to RD or WR Low t
LLWL
t
CLCL
-5 t
CLCL
+5
ns
t
MCS
>0
t
CLCL
-9 t
MCS
=0
Port 0 Address to RD or WR Low t
AVWL1
2t
CLCL
-7
ns
t
MCS
>0
1.5t
CLCL
-17 t
MCS
=0
Port 2 Address to RD or WR Low t
AVWL2
2.5t
CLCL
-16
ns
t
MCS
>0
Data Valid to WR Transition t
QVWX
-6 ns —
t
CLCL
-5 t
MCS
=0
Data Hold after Write t
WHQX
2t
CLCL
-6
ns
t
MCS
>0
RD Low to Address Float t
RLAZ
(Note 2) ns —
-4 10 t
MCS
=0
RD or WR High to ALE High t
WHLH
t
CLCL
-5 t
CLCL
+5
ns
t
MCS
>0
Note 1:
t
MCS
is a time period related to the Stretch memory cycle selection. The following table shows the value of t
MCS
for
each Stretch selection.
Note 2:
Address is driven strongly until ALE falls, and is then held in a weak latch until overdriven externally.