Datasheet
DS80C390 Dual CAN High-Speed Microprocessor
5 of 53
MOVX CHARACTERISTICS (MULTIPLEXED ADDRESS/DATA BUS) (Note 12)
PARAMETER SYMBOL MIN MAX UNITS
STRETCH
VALUES
C
ST
(MD2:0)
0.375 t
MCS
- 5 ns C
ST
= 0
0.5 t
MCS
- 5 ns
1 ≤ C
ST
≤ 3
MOVX ALE Pulse Width t
LHLL2
1.5 t
MCS
- 10 ns
4 ≤ C
ST
≤ 7
0.125 t
MCS
- 5 ns C
ST
= 0
0.25t
MCS
- 5 ns
1≤ C
ST
≤ 3
Port 0 MOVX Address, CE0–4,
PCE0–4 Valid to ALE Low
t
AVLL2
1.25 t
MCS
- 10 ns
4 ≤ C
ST
≤ 7
0.25t
MCS
-5 ns C
ST
= 0
0.125 t
MCS
- 5 ns
1≤ C
ST
≤ 3
Address Hold After MOVX
Read/Write
t
LLAX2
t
LLAX3
1.25 t
MCS
- 5 ns
4 ≤ C
ST
≤ 7
0.5 t
MCS
- 6 ns C
ST
= 0
RD Pulse Width
t
RLRH
C
ST
x t
MCS
- 10 ns
1 ≤ C
ST
≤ 7
0.5 t
MCS
- 6 ns C
ST
= 0
WR Pulse Width
t
WLWH
C
ST
x t
MCS
- 10 ns
1 ≤ C
ST
≤ 7
0.5 t
MCS
- 20 ns C
ST
= 0
RD Low to Valid Data In
t
RLDV
C
ST
x t
MCS
- 25 ns
1 ≤ C
ST
≤ 7
Data Hold After Read t
RHDX
0 ns
0.25 t
MCS
- 5 ns C
ST
= 0
0.5t
MCS
- 5
ns
1 ≤ C
ST
≤ 3
Data Float After Read t
RHDZ
1.5 t
MCS
- 5
ns
4 ≤ C
ST
≤ 7
0.625 t
MCS
- 20 ns C
ST
= 0
(C
ST
+ 0.25) x t
MCS
- 20 ns
1 ≤ C
ST
≤ 3
ALE Low to Valid Data In t
LLDV
(C
ST
+ 1.25) x t
MCS
- 20 ns
4 ≤ C
ST
≤ 7
0.75 t
MCS
- 26 ns C
ST
= 0
(4C
ST
+ 0.5) x t
MCS
- 30 ns
1≤ C
ST
≤ 3
Port 0 Address, Port 4 CE, Port 5
PCE to Valid Data In
t
AVDV1
(4C
ST
+ 2.5) x t
MCS
- 30 ns
4 ≤ C
ST
≤ 7
0.75 t
MCS
- 30 ns C
ST
= 0
(4C
ST
+ 0.5) x t
MCS
- 30 ns
1 ≤ C
ST
≤ 3
Port 2, 4 Address to Valid Data In t
AVDV2
(4C
ST
+ 2.5) x t
MCS
- 30 ns
4 ≤ C
ST
≤ 7
0.125 t
MCS
- 5 0.125 t
MCS
+ 10 ns C
ST
=0
0.25t
MCS
- 5 0.25t
MCS
+ 10 ns
1 ≤ C
ST
≤ 3
ALE Low to RD or WR Low
t
LLWL
1.25 t
MCS
- 5 1.25 t
MCS
+ 10 ns
4 ≤ C
ST
≤ 7
0.25 t
MCS
- 11 ns C
ST
= 0
0.5t
MCS
- 11 ns
1 ≤ C
ST
≤ 3
Port 0 Address, Port 4 CE, Port 5
PCE to RD or WR Low
t
AVWL1
2.5 t
MCS
- 11 ns
4 ≤ C
ST
≤ 7
0.375 t
MCS
- 11 ns C
ST
= 0
0.625t
MCS
- 11 ns
1 ≤ C
ST
≤ 3
Port 2, 4 Address to or WR Low
t
AVWL2
2.625 t
MCS
- 11 ns
4 ≤ C
ST
≤ 7
Data Valid to WR Transition
t
QVWX
-8 ns
0.25 t
MCS
- 8 ns C
ST
= 0
0.5t
MCS
- 10 ns
1 ≤ C
ST
≤ 3
Data Hold After WR High
t
WHQX
1.5 t
MCS
- 10 ns
4 ≤ C
ST
≤ 7
RD Low to Address Float
t
RLAZ
See Note 12
-5 +10 ns C
ST
= 0
0.25 t
MCS
- 7 0.25 t
MCS
+ 5 ns
1 ≤ C
ST
≤ 3
RD or WR High to ALE, Port 4 CE
or Port 5 PCE High
t
WHLH
1.25 t
MCS
- 7 1.25 t
MCS
+10 ns
4 ≤ C
ST
≤ 7
Note 12:
All parameters apply to both commercial and industrial temperature operation. C
ST
is the stretch cycle value determined by the
MD2:0 bits. t
MCS
is a time period shown in the t
MCS
Time Periods table. All signals characterized with load capacitance of 80pF
except Port 0, ALE, PSEN, RD, and WR with 100pF. Interfacing to memory devices with float times over 25ns can cause bus
contention and an increase in operating current. Specifications assume a 50% duty cycle for the oscillator; port 2 and ALE timing
changes in relation to duty cycle variation. Some AC timing characteristic drawings show the CLK signal, provided to determine the
relative occurrence of events and not the timing of signals relative to the external clock. During the external addressing mode, weak
latches maintain the previously driven value from the processor on Port 0 until Port 0 is overdriven by external memory; and on Port
1, 2 and 4 for one XTAL1 cycle prior to change in output address from Port 1, 2, and 4.