Datasheet
DS80C390 Dual CAN High-Speed Microprocessor
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Table 13. Interrupt Summary
NAME DESCRIPTION VECTOR
NATURAL
PRIORITY
FLAG BIT ENABLE BIT
PRIORITY
CONTROL BIT
PFI Power-Fail Interrupt 33h 0 PFI (WDCON.4) EPFI (WDCON.5) N/A
INT0 External Interrupt 0 03h 1 IE0 (TCON.1)** EX0 (IE.0) PX0 (IP.0)
TF0 Timer 0 0Bh 2 TF0 (TCON.5)* ET0 (IE.1) PT0 (IP.1)
INT1 External Interrupt 1 13h 3 IE1 (TCON.3)** EX1 (IE.2) PX1 (IP.2)
TF1 Timer 1 1Bh 4 TF1 (TCON.7)* ET1 (IE.3) PT1 (IP.3)
SCON0 TI0 or RI0 from Serial Port 0 23h 5
RI_0 (SCON0.0);
TI_0 (SCON0.1)
ES0 (IE.4) PS0 (IP.4)
TF2 Timer 2 2Bh 6 TF2 (T2CON.7) ET2 (IE.5) PT2 (IP.7)
SCON1 TI1 or RI1 from Serial Port 1 3Bh 7
RI_1 (SCON1.0);
TI_1 (SCON1.1)
ES1 (IE.6) PS1 (IP.6)
INT2 External Interrupt 2 43h 8 IE2 (EXIF.4) EX2 (EIE.0) PX2 (EIP.0)
INT3 External Interrupt 3 4Bh 9 IE3 (EXIF.5) EX3 (EIE.1) PX3 (EIP.1)
INT4 External Interrupt 4 53h 10 IE4 (EXIF.6) EX4 (EIE.2) PX4 (EIP.2)
INT5 External Interrupt 5 5Bh 11 IE5 (EXIF.7) EX5 (EIE.3) PX5 (EIP.3)
C0I CAN0 Interrupt 6Bh 12 various C0IE (EIE.6) C0IP (EIP.6)
C1I CAN1 Interrupt 73h 13 various C1IE (EIE.5) C1IP (EIP.5)
WDTI Watchdog Timer 63h 14 WDIF (WDCON.3) EWDI (EIE.4) PWDI (EIP.4)
CANBUS CAN0/1 Bus Activity 7Bh 15 various CANBIE (EIE.7) CANBIP (EIP.7)
Unless marked, all flags must be cleared by the application software.
*Cleared automatically by hardware when the service routine is entered.
**If edge-triggered, flag is cleared automatically by hardware when the service routine is entered. If level-triggered, flag follows the state of the
interrupt pin.
CONTROLLER AREA NETWORK (CAN) MODULE
The DS80C390 incorporates two CAN controllers that are fully compliant with the CAN 2.0B specification. CAN is a
highly robust, high-performance communication protocol for serial communications. Popular in a wide range of
applications including automotive, medical, heating, ventilation, and industrial control, the CAN architecture allows
for the construction of sophisticated networks with a minimum of external hardware.
The CAN controllers support the use of 11-bit standard or 29-bit extended acceptance identifiers for up to 15
messages, with the standard 8-byte data field, in each message. Fourteen of the 15 message centers are
programmable in either transmit or receive modes, with the 15th designated as a FIFO-buffered, receive-only
message center to help prevent data overruns. All message centers support two separate 8-bit media masks and
media arbitration fields for incoming message verification. This feature supports the use of higher-level protocols,
which make use of the first and/or second byte of data as a part of the acceptance layer for storing incoming
messages. Each message center can also be programmed independently to test incoming data with or without the
use of the global masks.
Global controls and status registers in each CAN unit allow the microcontroller to evaluate error messages,
generate interrupts, locate and validate new data, establish the CAN bus timing, establish identification mask bits,
and verify the source of individual messages. Each message center is individually equipped with the necessary
status and control bits to establish direction, identification mode (standard or extended), data field size, data status,
automatic remote frame request and acknowledgment, and perform masked or non-masked identification
acceptance testing.