Datasheet

DS80C390 Dual CAN High-Speed Microprocessor
44 of 53
POWER-FAIL RESET
The microcontroller incorporates an internal precision bandgap voltage reference and comparator circuit that
provide a power-on and power-fail reset function. This circuit monitors the processor’s incoming power supply
voltage (V
CC
), and holds the processor in reset while V
CC
is below the minimum voltage level. When power exceeds
the reset threshold, a full power-on reset is performed. In this way, this internal voltage monitoring circuitry handles
both power-up and power-down conditions without the need for additional external components.
Once V
CC
has risen above V
RST
, the device automatically restarts the oscillator for the external crystal and counts
65,536 clock cycles before program execution begins at location 0000h. This helps the system maintain reliable
operation by only permitting processor operation when the supply voltage is in a known good state. Software can
determine that a power-on reset has occurred by checking the power-on reset flag (POR;WDCON.6). Software
should clear the POR bit after reading it.
POWER-FAIL INTERRUPT
The bandgap voltage reference that sets a precise reset threshold also generates an optional early warning power-
fail interrupt (PFI). When enabled by software, the processor vectors to ROM address 0033h if V
CC
drops below
V
PFW
. PFI has the highest priority. The PFI enable is in the watchdog control SFR (EPFI;WDCON.5). Setting this bit
to logic 1 enables the PFI. Application software can also read the PFI flag at WDCON.4. A PFI condition sets this
bit to 1. The flag is independent of the interrupt enable and must be cleared by software.
EXTERNAL RESET PINS
The DS80C390 has reset input (RST) and reset output (RSTOL) pins. The RSTOL pin supplies an active-low reset
when the microprocessor is issued a reset from either a high on the RST pin, a timeout of the watchdog timer, a
crystal oscillator fail, or an internally detected power fail. The timing of the RSTOL pin is dependent on the source of
the reset.
RESET TYPE/SOURCE
RSTOL DURATION
Power-On Reset 65,536 t
CLCL
(as described in Power Cycle Timing Characteristics)
External Reset <1.25 machine cycles
Power Fail 65,536 t
CLCL
(as described in Power Cycle Timing Characteristics)
Watchdog Timer Reset 2 machine cycles
Oscillator-Fail Detect 65,536 t
CLCL
(as described in Power Cycle Timing Characteristics)
INTERRUPTS
The microcontroller provides 16 interrupt sources with three priority levels. All interrupts, with the exception of the
power-fail interrupt, are controlled by a series combination of individual enable bits and a global interrupt-enable,
EA (IE.7). Setting EA to 1 allows individual interrupts to be enabled. Clearing EA disables all interrupts regardless
of their individual enable settings.
The three available priority levels are low, high, and highest. The highest priority level is reserved for the power-fail
interrupt only. All other interrupt priority levels have individual priority bits that, when set to 1, establish the
particular interrupt as high priority. In addition to the user-selectable priorities, each interrupt also has an inherent
natural priority, used to determine the priority of simultaneously occurring interrupts. The available interrupt
sources, their flags, their enables, their natural priority, and their available priority selection bits are identified in
Table 13.