Datasheet

DS80C390 Dual CAN High-Speed Microprocessor
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Table 1. SFR Locations (continued)
REGISTER BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 ADDRESS
C0M14C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP BEh
C0M15C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP BFh
SCON1 SM0/FE_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 C0h
SBUF1 C1h
PMR CD1 CD0 SWB CTM
4X/2X
ALEOFF — — C4h
STATUS PIP HIP LIP — SPTA1 SPRA1 SPTA0 SPRA0 C5h
MCON IDM1 IDM0 CMA — PDCE3 PDCE2 PDCE1 PDCE0 C6h
TA C7h
T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2
C/T2 CP/RL2
C8h
T2MOD — — — D13T1 D13T2 —- T2OE DCEN C9h
RCAP2L CAh
RCAP2H CBh
TL2 CCh
TH2 CDh
COR IRDACK C1BPR7 C1BPR6 C0BPR7 C0BPR6 COD1 COD0 CLKOE CEh
PSW CY AC F0 RS1 RS0 OV F1 P D0h
MCNT0
LSHIFT
CSE SCB MAS4 MAS3 MAS2 MAS1 MAS0 D1h
MCNT1 MST MOF — CLM — — — — D2h
MA D3h
MB D4h
MC D5h
C1RMS0 D6h
C1RMS1 D7h
WDCON SMOD_1 POR EPFI PFI WDIF WTRF EWT RWT D8h
C1TMA0 DEh
C1TMA1 DFh
ACC E0h
C1C ERIE STIE PDE SIESTA CRST AUTOB ERCS SWINT E3h
C1S BSS CECE WKS RXS TXS ER2 ER1 ER0 E4h
C1IR INTIN7 INTIN6 INTIN5 INTIN4 INTIN3 INTIN2 INTIN1 INTIN0 E5h
C1TE E6h
C1RE E7h
EIE CANBIE C0IE C1IE EWDI EX5 EX4 EX3 EX2 E8h
MXAX EAh
C1M1C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP EBh
C1M2C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP ECh
C1M3C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP EDh
C1M4C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP EEh
C1M5C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP EFh
B F0h
C1M6C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP F3h
C1M7C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP F4h
C1M8C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP F5h
C1M9C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP F6h
C1M10C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP F7h
EIP CANBIP C0IP C1IP PWDI PX5 PX4 PX3 PX2 F8h
C1M11C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP FBh
C1M12C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP FCh
C1M13C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP FDh
C1M14C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP FEh
C1M15C MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP FFh
Note: Shaded bits are timed-access protected.