Datasheet

DS80C390 Dual CAN High-Speed Microprocessor
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AC ELECTRICAL CHARACTERISTICS—(MULTIPLEXED ADDRESS/DATA BUS)
(Note 10, Note 11)
40MHz VARIABLE CLOCK
PARAMETER SYMBOL CONDITIONS
MIN MAX MIN MAX
UNITS
External oscillator 0 40 0 40
Oscillator Frequency 1 / t
CLCL
External crystal 1 40 1 40
MHz
ALE Pulse Width t
LHLL
0.375 t
MCS
- 5
ns
Port 0 Instruction Address or CE0–4
Valid to ALE Low
t
AVLL
0.125 t
MCS
- 5 ns
Address Hold After ALE Low t
LLAX1
0.125 t
MCS
- 5 ns
ALE Low to Valid Instruction In t
LLIV
0.625 t
MCS
- 20 ns
ALE Low to PSEN Low
t
LLPL
0.125 t
MCS
- 5 ns
PSEN Pulse Width
t
PLPH
0.5 t
MCS
- 8 ns
PSEN Low to Valid Instruction In
t
PLIV
0.5 t
MCS
- 20 ns
Input Instruction Hold After PSEN
t
PXIX
0 0 ns
Input Instruction Float After PSEN
t
PXIZ
0.25 t
MCS
- 5 ns
Port 0 Address to Valid Instruction In t
AVIV1
0.75 t
MCS
- 22 ns
Port 2, 4 Address to Valid Instruction
In
t
AVIV2
0.875 t
MCS
- 30 ns
PSEN Low to Address Float
t
PLAZ
0 0 ns
Note 11: All parameters apply to both commercial and industrial temperature operation unless otherwise noted. The value t
MCS
is a function
of the machine cycle clock in terms of the processor’s input clock frequency. These relationships are described in the Stretch Value
Timing table. All signals characterized with load capacitance of 80pF except Port 0, ALE, PSEN, RD, and WR with 100pF.
Interfacing to memory devices with float times (turn off times) over 25ns can cause bus contention. This does not damage the
parts, but causes an increase in operating current. Specifications assume a 50% duty cycle for the oscillator. Port 2 and ALE timing
changes in relation to duty cycle variation. Some AC timing characteristic drawings contain references to the CLK signal. This
waveform is provided to assist in determining the relative occurrence of events and cannot be used to determine the timing of
signals relative to the external clock. AC timing is characterized and guaranteed by design but is not production tested.