Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 64 (10x10) 8-Bit 40 MHz I/O number 32

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REV: 110905

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata

GENERAL DESCRIPTION

The DS80C390 is a fast 8051-compatible

microprocessor with dual CAN 2.0B controllers. The

redesigned processor core executes 8051

instructions up to 3X faster than the original for the

same crystal speed. The DS80C390 supports a

maximum crystal speed of 40MHz, resulting in

apparent execution speeds of 100MHz

(approximately 2.5X). An optional internal frequency

multiplier allows the microprocessor to operate at full

speed with a reduced crystal frequency, reducing

EMI. A hardware math accelerator further increases

the speed of 32-bit and 16-bit multiply and divide

operations as well as high-speed shift, normalization,

and accumulate functions.

The High-Speed Microcontroller User’s Guide and High-Speed

Microcontroller User’s Guide: DS80C390 Supplement must be

used in conjunction with this data sheet. Download both at:

www.maxim-ic.com/microcontrollers.

APPLICATIONS

Industrial Controls Agricultural Equipment

Factory Automation Gaming Equipment

Medical Equipment

Automotive

Heating, Ventilation, and

Air Conditioning

FEATURES

 80C52 Compatible

 High-Speed Architecture

 4kB Internal SRAM Usable as Program/

Data/Stack Memory

 Enhanced Memory Architecture

 Two Full-Function CAN 2.0B Controllers

 Two Full-Duplex Hardware Serial Ports

 Programmable IrDA Clock

 High Integration Controller

 16 Interrupt Sources with Six External

 Available in 64-Pin LQFP, 68-Pin PLCC

See page 29 for a complete list of features.

ORDERING INFORMATION

PART TEMP RANGE PIN-PACKAGE

DS80C390-QCR 0°C to +70°C 68 PLCC

DS80C390-QCR+ 0°C to +70°C 68 PLCC

DS80C390-QNR -40°C to +85°C 68 PLCC

DS80C390-QNR+ -40°C to +85°C 68 PLCC

DS80C390-FCR 0°C to +70°C 64 LQFP

DS80C390-FCR+ 0°C to +70°C 64 LQFP

DS80C390-FNR -40°C to +85°C 64 LQFP

DS80C390-FNR+ -40°C to +85°C 64 LQFP

+Denotes a lead(Pb)-free/RoHS-compliant device.

PIN CONFIGURATIONS

DS80C390

Dual CAN High-Speed Microprocesso

www.maxim-ic.com

Dallas Semiconductor

DS80C390

PLCC

Dallas Semiconductor

DS80C390

48 33

16 1

LQFP

TOP VIEW

Summary of content (53 pages)

PAGE 1
DS80C390 Dual CAN High-Speed Microprocessor www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS80C390 is a fast 8051-compatible microprocessor with dual CAN 2.0B controllers. The redesigned processor core executes 8051 instructions up to 3X faster than the original for the same crystal speed. The DS80C390 supports a maximum crystal speed of 40MHz, resulting in apparent execution speeds of 100MHz (approximately 2.5X).
PAGE 2
DS80C390 Dual CAN High-Speed Microprocessor ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground……………………………………………………….-0.3V to (VCC + 0.5V) Voltage Range on VCC Relative to Ground……………………………………………………………………-0.3V to +6.0V Operating Temperature Range………………………………………………………………………………..-40°C to +85°C Storage Temperature Range………………………………………………………………………………...-55°C to +125°C Soldering Temperature…..……………………………………………………………………..
PAGE 3
DS80C390 Dual CAN High-Speed Microprocessor AC ELECTRICAL CHARACTERISTICS—(MULTIPLEXED ADDRESS/DATA BUS) (Note 10, Note 11) PARAMETER Oscillator Frequency SYMBOL CONDITIONS 1 / tCLCL External oscillator External crystal 40MHz MIN MAX 0 40 1 40 VARIABLE CLOCK MIN MAX 0 40 1 40 0.375 tMCS -5 UNITS MHz ALE Pulse Width tLHLL Port 0 Instruction Address or CE0–4 Valid to ALE Low tAVLL 0.125 tMCS - 5 ns Address Hold After ALE Low tLLAX1 0.
PAGE 4
DS80C390 Dual CAN High-Speed Microprocessor AC SYMBOLS The DS80C390 uses timing parameters and symbols similar to the original 8051 family. The following list of timing symbols is provided as an aid to understanding the timing diagrams. SYMBOL t A C CE D H L I P Q R V W X Z FUNCTION Time Address Clock Chip Enable Input Data Logic Level High Logic Level Low Instruction PSEN Output Data RD Signal Valid WR Signal No longer a valid logic level. Tri-State Figure 1.
PAGE 5
DS80C390 Dual CAN High-Speed Microprocessor MOVX CHARACTERISTICS (MULTIPLEXED ADDRESS/DATA BUS) (Note 12) PARAMETER SYMBOL MIN MAX UNITS 0.5 tMCS - 20 CST x tMCS - 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.375 tMCS - 5 0.5 tMCS - 5 1.5 tMCS - 10 0.125 tMCS - 5 0.25tMCS - 5 1.25 tMCS - 10 0.25tMCS-5 0.125 tMCS - 5 1.25 tMCS - 5 0.5 tMCS - 6 CST x tMCS - 10 0.
PAGE 6
DS80C390 Dual CAN High-Speed Microprocessor Figure 2.
PAGE 7
DS80C390 Dual CAN High-Speed Microprocessor Figure 3.
PAGE 8
DS80C390 Dual CAN High-Speed Microprocessor Figure 4. Multiplexed 2-Cycle Data Memory PCE0-3 Read or Write Figure 5.
PAGE 9
DS80C390 Dual CAN High-Speed Microprocessor Figure 6. Multiplexed 2-Cycle Data Memory CE0-3 Write Figure 7.
PAGE 10
DS80C390 Dual CAN High-Speed Microprocessor Figure 8. Multiplexed 3-Cycle Data Memory CE0-3 Read Figure 9.
PAGE 11
DS80C390 Dual CAN High-Speed Microprocessor Figure 10. Multiplexed 9-Cycle Data Memory PEC0-3 Read or Write Figure 11.
PAGE 12
DS80C390 Dual CAN High-Speed Microprocessor Figure 12.
PAGE 13
DS80C390 Dual CAN High-Speed Microprocessor ELECTRICAL CHARACTERISTICS—(NONMULTIPLEXED ADDRESS/DATA BUS) (Note 13) PARAMETER Oscillator Frequency SYMBOL 1 / tCLCL CONDITIONS External oscillator External crystal 40MHz MIN MAX 0 40 1 40 VARIABLE CLOCK MIN MAX 0 40 1 40 UNITS MHz PSEN Pulse Width tPLPH PSEN Low to Valid Instruction In tPLIV Input Instruction Hold After PSEN tPXIX Input Instruction Float After PSEN tPXIZ See MOVX Characteristics ns tAVIV1 0.75 tMCS - 22 ns tAVIV2 0.
PAGE 14
DS80C390 Dual CAN High-Speed Microprocessor MOVX CHARACTERISTICS (NONMULTIPLEXED ADDRESS/DATA BUS) PARAMETER SYMBOL RD Pulse Width tRLRH WR Pulse Width tWLWH RD Low to Valid Data In tRLDV Data Hold After Read tRHDX Data Float After Read tRHDZ Port 1 Address, Port 4 CE, Port 5 PCE to Valid Data In tAVDV1 Port 2, 4 Address to Valid Data In tAVDV2 Port 0 Address, Port 4 CE, Port 5 PCE to RD or WR Low tAVWL1 Port 2, 4 Address to RD or WR Low tAVWL2 Data Valid to WR Transition tQVWX Data H
PAGE 15
DS80C390 Dual CAN High-Speed Microprocessor Figure 14.
PAGE 16
DS80C390 Dual CAN High-Speed Microprocessor Figure 15.
PAGE 17
DS80C390 Dual CAN High-Speed Microprocessor Figure 16. Nonmultiplexed 2-Cycle Data Memory PCE0 - 3 Read or Write Figure 17.
PAGE 18
DS80C390 Dual CAN High-Speed Microprocessor Figure 18. Nonmultiplexed 2-Cycle Data Memory CE0-3 Write Figure 19.
PAGE 19
DS80C390 Dual CAN High-Speed Microprocessor Figure 20. Nonmultiplexed 3-Cycle Data Memory CE0-3 Read Figure 21.
PAGE 20
DS80C390 Dual CAN High-Speed Microprocessor Figure 22. Nonmultiplexed 9-Cycle Data Memory PCE0-3 Read or Write Figure 23.
PAGE 21
DS80C390 Dual CAN High-Speed Microprocessor Figure 24. Nonmultiplexed 9-Cycle Data Memory CE0-3 Write tMCS TIME PERIODS SYSTEM CLOCK SELECTION tMCS 4X/2X CD1 CD0 1 0 X X 0 0 1 1 0 0 0 1 1 tCLCL 2 tCLCL 4 tCLCL 1024 tCLCL EXTERNAL CLOCK CHARACTERISTICS PARAMETER Clock High Time Clock Low Time Clock Rise Time Clock Fall Time SYMBOL tCHCX tCLCX tCLCH tCHCL MIN 8 8 MAX 4 4 Figure 25.
PAGE 22
DS80C390 Dual CAN High-Speed Microprocessor SERIAL PORT MODE 0 TIMING CHARACTERISTICS PARAMETER SYMBOL Serial Port Clock Cycle Time tXLXL Output Data Setup to Clock Rising tQVXH Output Data Hold from Clock Rising tXHQX Input Data Hold After Clock Rising tXHDX Clock Rising Edge to Input Data Valid tXHDV CONDITIONS SM2 = 0:2 clocks per cycle SM2 = 1:4 clocks per cycle SM2 = 0:12 clocks per cycle SM2 = 1:4 clocks per cycle M2 = 0:12 clocks per cycle SM2 = 1:4 clocks per cycle SM2 = 0:12 clocks per
PAGE 23
DS80C390 Dual CAN High-Speed Microprocessor Figure 26.
PAGE 24
DS80C390 Dual CAN High-Speed Microprocessor POWER-CYCLE TIMING CHARACTERISTICS PARAMETER SYMBOL TYP Crystal Startup Time (Note 14) tCSU 1.8 Power-On Reset Delay (Note 15) tPOR MAX UNITS ms 65,536 tCLCL Note 14: Startup time for crystals varies with load capacitance and manufacturer. Time shown is for an 11.0592MHz crystal manufactured by Fox Electronics. Note 15: Reset delay is a synchronous counter of crystal oscillations during crystal startup.
PAGE 25
DS80C390 Dual CAN High-Speed Microprocessor PIN DESCRIPTION PIN LQFP 8, 22, 40, 56 9, 25, 41, 57 PLCC 17, 32, 51, 68 1, 18, 35, 52 NAME VCC GND 46 57 ALE 45 56 PSEN 47 58 EA 26 36 MUX 2 11 RST 3 12 RSTOL 23 33 XTAL2 24 34 XTAL1 55 54 53 52 51 50 49 48 67 66 65 64 63 62 61 59 AD0/D0 AD1/D1 AD2/D2 AD3/D3 AD4/D4 AD5/D5 AD6/D6 AD7/D7 FUNCTION +5V Digital Circuit Ground Address Latch Enable, Output.
PAGE 26
DS80C390 Dual CAN High-Speed Microprocessor PIN DESCRIPTION (continued) PIN LQFP 58–64, 1 58 59 60 61 62 63 64 1 35 36 37 38 39 42 43 44 PLCC 2–8, 10 2 3 4 5 6 7 8 10 46 47 48 49 50 53 54 55 4–7, 10–13 13–16, 19–22 4 5 6 7 10 11 12 13 13 14 15 16 19 20 21 22 NAME FUNCTION P1.0–P1.7 Port 1, I/O. Port 1 can function as an 8-bit bidirectional I/O port, the nonmultiplexed A0–A7 signals (when the MUX pin = 1), and as an alternate interface for internal resources.
PAGE 27
DS80C390 Dual CAN High-Speed Microprocessor PIN DESCRIPTION (continued) PIN LQFP PLCC 34–27 45, 44, 42–37 34 33 32 31 30 29 28 27 45 44 42 41 40 39 38 37 21–14 31–27, 25–23 21 20 19 18 17 16 15 14 31 30 29 28 27 25 24 23 9, 26, 43, 60 NAME FUNCTION P4.0–P4.7 Port 4, I/O. Port 4 can function as an 8-bit, bidirectional I/O port, and as the source for external address and chip enable signals for program and data memory. Port pins are configured as I/O or memory signals via the P4CNT register.
PAGE 28
DS80C390 Dual CAN High-Speed Microprocessor Figure 28.
PAGE 29
DS80C390 Dual CAN High-Speed Microprocessor FEATURES 80C52 Compatible 8051-Instruction-Set Compatible Four 8-Bit I/O Ports Three 16-Bit Timer/Counters 256 Bytes Scratchpad RAM High-Speed Architecture 4 Clocks/Machine Cycle (8051 = 12) Runs DC to 40MHz Clock Rates Frequency Multiplier Reduces Electromagnetic Interference (EMI) Single-Cycle Instruction in 100ns 16/32-Bit Math Coprocessor 4kB Internal SRAM Usable as Program/Data/Stack Memory Enhanced Memory Architecture Addresses Up to 4MB External Defaults t
PAGE 30
DS80C390 Dual CAN High-Speed Microprocessor Because the device runs the standard 8051 instruction set, in general, software written for existing 80C32-based systems will work on the DS80C390. The primary exceptions are related to timing-critical issues, since the highperformance core of the microcontroller executes instructions much faster than the original. Memory interfacing is performed identically to the standard 80C32.
PAGE 31
DS80C390 Dual CAN High-Speed Microprocessor Table 1. SFR Locations REGISTER BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 ADDRESS P4 SP DPL DPH DPL1 DPH1 DPS PCON TCON TMOD TL0 TL1 TH0 TH1 CKCON P1 EXIF P4CNT DPX DPX1 C0RMS0 C0RMS1 SCON0 SBUF0 ESP AP ACON C0TMA0 C0TMA1 P2 P5 P5CNT C0C C0S C0IR C0TE C0RE IE SADDR0 SADDR1 C0M1C C0M2C C0M3C C0M4C C0M5C P3 C0M6C C0M7C C0M8C C0M9C C0M10C IP SADEN0 SADEN1 C0M11C C0M12C C0M13C P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.
PAGE 32
DS80C390 Dual CAN High-Speed Microprocessor Table 1.
PAGE 33
DS80C390 Dual CAN High-Speed Microprocessor ON-CHIP ARITHMETIC ACCELERATOR An on-chip math accelerator allows the microcontroller to perform 32-bit and 16-bit multiplication, division, shifting, and normalization using dedicated hardware. Math operations are performed by sequentially loading three special registers. The mathematical operation is determined by the sequence in which three dedicated SFRs (MA, MB, and MC) are accessed, eliminating the need for a special step to choose the operation.
PAGE 34
DS80C390 Dual CAN High-Speed Microprocessor 40-BIT ACCUMULATOR The accelerator also incorporates an automatic accumulator function, permitting the implementation of multiplyand-accumulate and divide-and-accumulate functions without any additional delay. Each time the accelerator is used for a multiply or divide operation, the result is transparently added to a 40-bit accumulator. This can greatly increase speed of DSP and other high-level math operations.
PAGE 35
DS80C390 Dual CAN High-Speed Microprocessor INTERNAL MOVX SRAM The DS80C390 contains 4kB of SRAM that can be configured as user accessible MOVX memory, program memory, or optional stack memory. The specific configuration and locations are governed by the internal data memory configuration bits (IDM1, IDM0) in the memory control register (MCON;C6h). Note that when the SA bit (ACON.2) is set, the first 1kB of the MOVX data memory is reserved for use by the 10-bit expanded stack.
PAGE 36
DS80C390 Dual CAN High-Speed Microprocessor Table 8. Program Memory Chip-Enable Boundaries P4CNT.5–3 CE0 CE1 CE2 CE3 000 100 101 110 111(default) 0h–7FFFh 0h–1FFFFh 0h–3FFFFh 0h–7FFFFh 0–FFFFFh 8000h–FFFFh 20000h–3FFFFh 40000h–7FFFFh 80000h–FFFFFh 100000h–1FFFFFh 10000h–17FFFh 40000h–5FFFFh 80000h–BFFFFh 100000h–17FFFFh 200000h–2FFFFFh 18000h–1FFFFh 60000h–7FFFFh C0000h–FFFFFh 180000h–1FFFFFh 300000h–3FFFFFh The DS80C390 incorporates a feature allowing PCE and CE signals to be combined.
PAGE 37
DS80C390 Dual CAN High-Speed Microprocessor Table 9. Data Memory Cycle Stretch Values MD2 MD1 MD0 STRETCH CYCLE COUNT 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0* 1** 2 3 4 5 6 7 MOVX MACHINE CYCLES 2 3 4 5 9 10 11 12 RD, WR PULSE WIDTH (IN OSCILLATOR CLOCKS) tMCS (4X/2X = 1 CD1:0 = 00) 0.
PAGE 38
DS80C390 Dual CAN High-Speed Microprocessor INC DPTR MOV DPTR, #data16 MOVC A, @A+DPTR MOVX A, @DPTR MOVX @DPTR, A As a brief example, if TSL is set to 1, then both data pointers can be updated with two INC DPTR instructions. Assume that SEL = 0, making DPTR the active data pointer. The first INC DPTR increments DPTR and toggles SEL to 1. The second instruction increments DPTR1 and toggles SEL back to 0.
PAGE 39
DS80C390 Dual CAN High-Speed Microprocessor the microcontroller can never be operated faster than 40MHz. This means that the maximum crystal oscillator or external clock source is 10MHz when using the 4X setting, and 20MHz when using the 2X setting. The primary advantage of the clock multiplier is that it allows the microcontroller to use slower crystals to achieve the same performance level. This reduces EMI and cost, as slower crystals are generally more available and thus less expensive. Table 11.
PAGE 40
DS80C390 Dual CAN High-Speed Microprocessor POWER MANAGEMENT MODE (PMM) AND SWITCHBACK Power consumption in PMM is less than in idle mode, and approximately one quarter of that consumed in divideby-four mode. While PMM and Idle modes leave the power-hungry internal timers running, PMM runs all clocked functions such as timers at the rate of crystal divided by 1024, rather than crystal divided by 4.
PAGE 41
DS80C390 Dual CAN High-Speed Microprocessor STOP MODE Setting the STOP bit of the power control register (PCON.1) invokes stop mode. Stop mode is the lowest power state (besides power off) since it turns off all internal clocking. All processor operation ceases at the end of the instruction that sets the STOP bit. The CPU can exit stop mode via an external interrupt, if enabled, or a reset condition.
PAGE 42
DS80C390 Dual CAN High-Speed Microprocessor TIMED-ACCESS PROTECTION Selected SFR bits are critical to operation, making it desirable to protect them against an accidental write operation. The timed-access procedure prevents an errant processor from accidentally altering bits that would seriously affect processor operation.
PAGE 43
DS80C390 Dual CAN High-Speed Microprocessor The SCON0 register provides control for serial port 0 while its I/O buffer is SBUF0. The registers SCON1 and SBUF1 provide the same functions for the second serial port. A full description of the use and operation of both serial ports can be found in the High-Speed Microcontroller User’s Guide: DS80C390 Supplement.
PAGE 44
DS80C390 Dual CAN High-Speed Microprocessor POWER-FAIL RESET The microcontroller incorporates an internal precision bandgap voltage reference and comparator circuit that provide a power-on and power-fail reset function. This circuit monitors the processor’s incoming power supply voltage (VCC), and holds the processor in reset while VCC is below the minimum voltage level. When power exceeds the reset threshold, a full power-on reset is performed.
PAGE 45
DS80C390 Dual CAN High-Speed Microprocessor Table 13.
PAGE 46
DS80C390 Dual CAN High-Speed Microprocessor COMMUNICATING WITH THE CAN MODULE The microcontroller interface to the CAN modules is divided into two groups of registers. All the global CAN status and control bits as well as the individual message center control/status registers are located in the SFR map. The remaining registers associated with the message centers (data identification, identification/arbitration masks, format, and data) are located in MOVX data space. The CMA bit (MCON.
PAGE 47
DS80C390 Dual CAN High-Speed Microprocessor MOVX MESSAGE CENTERS FOR CAN 0 CAN 0 CONTROL/STATUS/MASK REGISTERS REGISTER 7 6 5 4 3 2 1 0 C0MID0 C0MA0 C0MID1 C0MA1 C0BT0 C0BT1 C0SGM0 C0SGM1 C0EGM0 C0EGM1 C0EGM2 C0EGM3 C0M15M0 C0M15M1 C0M15M2 C0M15M3 MID07 M0AA7 MID17 M1AA7 SJW1 SMP ID28 ID20 ID28 ID20 ID12 ID4 ID28 ID20 ID12 ID4 MID06 M0AA6 MID16 M1AA6 SJW0 TSEG26 ID27 ID19 ID27 ID19 ID11 ID3 ID27 ID19 ID11 ID3 MID05 M0AA5 MID15 M1AA5 BPR5 TSEG25 ID26 ID18 ID26 ID18 ID10 ID2 ID26 ID18 ID10 ID2 M
PAGE 48
DS80C390 Dual CAN High-Speed Microprocessor MOVX MESSAGE CENTERS FOR CAN 1 CAN 1 CONTROL/STATUS/MASK REGISTERS REGISTER 7 6 5 4 3 2 1 0 C1MID0 C1MA0 C1MID1 C1MA1 C1BT0 C1BT1 C1SGM0 C1SGM1 C1EGM0 C1EGM1 C1EGM2 C1EGM3 C1M15M0 C1M15M1 C1M15M2 C1M15M3 MID07 M0AA7 MID17 M1AA7 SJW1 SMP ID28 ID20 ID28 ID20 ID12 ID4 ID28 ID20 ID12 ID4 MID06 M0AA6 MID16 M1AA6 SJW0 TSEG26 ID27 ID19 ID27 ID19 ID11 ID3 ID27 ID19 ID11 ID3 MID05 M0AA5 MID15 M1AA5 BPR5 TSEG25 ID26 ID18 ID26 ID18 ID10 ID2 ID26 ID18 ID10 ID2 M
PAGE 49
DS80C390 Dual CAN High-Speed Microprocessor CAN INTERRUPTS The DS80C390 supports three interrupts associated with the CAN controllers. One interrupt is dedicated to each CAN controller, providing receive/transmit acknowledgments from each of its 15 message centers. The remaining interrupt, the CAN bus activity interrupt, is used to detect CAN bus activity on the C0RX or C1RX pins.
PAGE 50
DS80C390 Dual CAN High-Speed Microprocessor Table 14. Arbitration/Masking Feature Summary TEST NAME ARBITRATION REGISTERS MASK REGISTERS CONTROL BITS AND CONDITIONS Standard 11-Bit Arbitration (CAN 2.0A) Message Center Arbitration Registers 0–1 (Located in each Message Center, MOVX memory) Standard Global Mask Registers 0–1 (Located in each CAN Control/Status/Mask Register bank, MOVX memory) EX/ST = 0 MEME = 0: Mask register ignored. ID and arbitration register must match exactly.
PAGE 51
DS80C390 Dual CAN High-Speed Microprocessor MESSAGE BUFFERING/OVERWRITE If a message center is configured for reception (T/R = 0) and the previous message has not been read (DTUP = 1), then the disposition of an incoming message to that message center is controlled by the WTOE bit (located in CAN Arbitration Register 3 of each message center). When WTOE = 0, the incoming message is discarded and the current message is untouched.
PAGE 52
DS80C390 Dual CAN High-Speed Microprocessor PACKAGE INFORMATION For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
PAGE 53
DS80C390 Dual CAN High-Speed Microprocessor REVISION HISTORY REVISION 062299 090799 110199 032904 DESCRIPTION Initial preliminary release. Clarifies that unused/unimplemented bits in the CAN MOVX SRAM read 0. Corrected the tMCS time period table. Corrected multiplexed 2-cycle date memory CEO-3 read figure to show RD and WR inactive. Corrected P5.2 and P5.3 pin descriptions. Corrected description of sequence to activate the crystal frequency multiplier. Corrected references to PQFP to read LQFP.