Datasheet

DS80C310
14 of 22
MOVX CHARACTERISTICS
VARIABLE CLOCK
PARAMETER SYMBOL
MIN MAX
UNITS
STRETCH
(Note 1)
1.5t
CLCL
-5 t
MCS
=0
Data Access ALE Pulse Width t
LHLL2
2t
CLCL
-5
ns
t
MCS
>0
0.5t
CLCL
-5 t
MCS
=0
Port 0 Address Valid to ALE Low t
AVLL2
t
CLCL
-5
ns
t
MCS
>0
0.5t
CLCL
-15 t
MCS
=0
Address Hold after ALE Low for
MOVX Write
t
LLAX2
t
CLCL
-7
ns
t
MCS
>0
2t
CLCL
-5 t
MCS
=0
RD Pulse Width
t
RLRH
t
MCS
-10
ns
t
MCS
>0
2t
CLCL
-5 t
MCS
=0
WR Pulse Width
t
WLWH
t
MCS
-10
ns
t
MCS
>0
2t
CLCL
-20 t
MCS
=0
RD Low to Valid Data In
t
RLDV
t
MCS
-20
ns
t
MCS
>0
Data Hold after Read t
RHDX
0 ns
t
CLCL
-5 t
MCS
=0
Data Float after Read t
RHDZ
2t
CLCL
-5
ns
t
MCS
>0
2.5t
CLCL
-28 t
MCS
=0
ALE Low to Valid Data In t
LLDV
t
CLCL
+t
MCS
-40
ns
t
MCS
>0
3t
CLCL
-22 t
MCS
=0
Port 0 Address to Valid Data In t
AVDV1
2.0t
CLCL+
t
MCS
-
25
ns
t
MCS
>0
3.5t
CLCL
-35 t
MCS
=0
Port 2 Address to Valid Data In t
AVDV2
2.5t
CLCL+
t
MCS
-
35
ns
t
MCS
>0
0.5t
CLCL
-14 0.5t
CLCL
+5 t
MCS
=0
ALE Low to RD or WR Low
t
LLWL
t
CLCL
-8 t
CLCL
+5
ns
t
MCS
>0
t
CLCL
-9 t
MCS
=0
Port 0 Address to RD or WR Low
t
AVWL1
2t
CLCL
-8
ns
t
MCS
>0
1.5t
CLCL
-10 t
MCS
=0
Port 2 Address to RD or WR Low
t
AVWL2
2.5t
CLCL
-10
ns
t
MCS
>0
Data Valid to WR Transition
t
QVWX
-14 ns
t
CLCL
-11 t
MCS
=0
Data Hold after Write t
WHQX
2t
CLCL
-10
ns
t
MCS
>0
RD Low to Address Float
t
RLAZ
(Note 2) ns
0 10 t
MCS
=0
RD or WR High to ALE High
t
WHLH
t
CLCL
-5 t
CLCL
+9
ns
t
MCS
>0
Note 1:
t
MCS
is a time period related to the stretch memory cycle selection. The following table shows the value of t
MCS
for each
stretch selection.
M2 M1 M0 MOVX CYCLES t
MCS
0 0 0 2 machine cycles 0
0 0 1 3 machine cycles (default) 4 t
CLCL
0 1 0 4 machine cycles 8 t
CLCL
0 1 1 5 machine cycles 12 t
CLCL
1 0 0 6 machine cycles 16 t
CLCL
1 0 1 7 machine cycles 20 t
CLCL
1 1 0 8 machine cycles 24 t
CLCL
1 1 1 9 machine cycles 28 t
CLCL