Datasheet

DS80C310

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Note 6:

When addressing external memory. This specification applies to the first clock cycle following the transition. On subsequent

cycles following 1 to 0 transitions, the typical current sink capability of Port 0 and Port 2 is approximately 150A, and the

minimum current sink capability of ALE and PSEN is approximately 400A. On subsequent cycles following 0 to 1

transitions, the typical current drive capability of Port 0 and Port 2 is approximately 110A.

Note 7:

RST = V

. This condition mimics operation of pins in I/O mode.

Note 8:

During a 0 to 1 transition, a one-shot drives the ports hard for two clock cycles. This measurement reflects port in transition

mode.

Note 9:

Current required from external circuit to hold a logic-low level on an I/O pin while the corresponding port latch bit is set to 1.

This is only the current required to hold the low level; transitions from 1 to 0 on an I/O pin must also overcome the transition

current.

Note 10:

Ports 1 and 3 source transition current when being pulled down externally. The current reaches its maximum at approximately

2V.

Note 11:

0.45 < V

. Not a high-impedance input. This port is a weak address holding latch because Port 0 is dedicated as an

address bus on the DS80C310. Peak current occurs near the input transition point of the latch, approximately 2V.

Figure 2. Typical I

vs. Frequency