Datasheet

DS8007
Multiprotocol Dual Smart Card Interface
34 ______________________________________________________________________________________
parameters continue to be used until a successful PPS
exchange is completed. The negotiated Fn, Dn values
are then used after a successful PPS exchange. If the
card comes up in specific mode (i.e., TA(2) is present
in ATR), then the indicated Fi, Di values apply immedi-
ately after successful ATR if bit 5 of the TA(2) charac-
ter is 0. If bit 5 of TA(2) is 1, implicit values should be
used. The TA(1) character of ATR, if present, contains
the Fi and Di values indicated by the card.
Table 5 demonstrates how the prescaler (PSC) bit and
programmable divider register (PDRx) can be config-
ured to generate the requested F/D ratios. All settings
assume that the CKU bit is configured to its reset
default logic 0 state.
Table 4. Fi, Di Parameter Possibilities
TA(1).Fi Fi MAX CLKx (MHz) Fi = TA(1).Di Di
0000 372 4 31 x 12 0000 RFU
0001 372 5 31 x 12 0001 1
0010 558 6 31 x 18 0010 2
0011 744 8 31 x 24 0011 4
0100 1116 12 31 x 36 0100 8
0101 1488 16 31 x 48 0101 16
0110 1860 20 31 x 60 0110 32
0111 RFU — — 0111 RFU
1000 RFU — — 1000 RFU
1001 512 5 32 x 16 1001 12
1010 768 7.5 32 x 24 1010 20
1011 1024 10 32 x 32 1011 RFU
1100 1536 15 32 x 48 1100 RFU
1101 2048 20 32 x 64 1101 RFU
1110 RFU RFU — 1110 RFU
1111 RFU RFU — 1111 RFU
RFU = Reserved for future use.
Table 5. PSC, PDR Settings to Support F, D Parameters
PDR SETTING FOR Di =
TA(1).Fi
PSC
0 = /31
1 = /32
0001 0010 0011 0100 0101 0110 1000 1001
0000 0 12 6 3 — — — 1 —
0001 0 12 6 3 — — — 1 —
0010 0 18 9 — — — — — —
0011 0 24 12 6 3 — — 2 —
0100 0 36 18 9 — — — 3 —
0101 0 48 24 12 6 3 — 4 —
0110 0 60 30 15 — — — 53
1001 1 16 8 4 2 1 — — —
1010 1 24 12 6 3 — — 2 —
1011 1 32 16 8 4 2 1 — —
1100 1 48 24 12 6 3 — 4 —
1101 1 64 32 16 8 4 2 — —