Datasheet

DS75LX: Digital Thermometer and Thermostat with Extended Addressing
3 of 13
SCL Frequency f
SCL
400 kHz
AC ELECTRICAL CHARACTERISTICS (continued)
(1.7V ≤ V
DD
≤ 3.7V, T
A
= -55°C to +125°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Bus Free Time Between
a STOP and START
Condition
t
BUF
(Note 7)
1.3
µs
START and Repeated
START Hold Time from
Falling SCL
t
HD:STA
(Notes 7, 8)
600
ns
Low Period of SCL t
LOW
(Note 7) 1.3 µs
High Period of SCL t
HIGH
(Note 7) 0.6 µs
Repeated START
Condition Setup Time to
Rising SCL
t
SU:STA
(Note 7) 600 ns
Data-Out Hold Time from
Falling SCL
t
HD:DAT
(Notes 7, 9) 0 0.9 µs
Data-In Setup Time to
Rising SCL
t
SU:DAT
(Note 7)
100
ns
Rise Time of SDA and
SCL (Receive)
t
R
(Notes 7, 10)
20 +
0.1C
B
B
300 ns
Fall Time of SDA and
SCL (Receive)
t
F
(Notes 7, 10)
20 +
0.1C
B
B
300 ns
Spike Suppression
Filter Time (Deglitch
Filter)
t
SS
0 50 ns
STOP Setup Time to
Rising SCL
t
SU:STO
(Note 7) 600 ns
Capacitive Load for Each
Bus Line
C
B
B 400 pF
Input Capacitance C
I
5 pF
Serial Interface Reset
Time
t
TIMEOUT
SDA time low
(Notes 11, 12)
75 325 ms
Note 1: V
DD
must be decoupled with a high-quality 0.1µF bypass capacitor. X5R or X7R ceramic surface-mount capacitors are
recommended.
Note 2:
Internal heating caused by O.S. loading causes the DS75LX to read approximately 0.5°C higher if O.S. is sinking the max
rated current.
Note 3: All voltages are referenced to ground.
Note 4: I
DD
specified with O.S. pin open and A0–A2 pins grounded.
Note 5:
I
DD
and address leakage specified with V
DD
at 3.0V and SDA, SCL = 3.0V at 0°C to +70°C.
Note 6: Address pins A0, A1, A2 are directly connected to V
DD
, V
SS
, or floating with less than 50pF capacitive load.
Note 7: See the timing diagram (Figure 1). All timing is referenced to 0.9 x V
DD
and 0.1 x V
DD
.
Note 8: After this period, the first clock pulse is generated.
Note 9: The DS75LX provides an internal hold time of at least 75ns on the SDA signal to bridge the undefined region of SCL's falling
edge.
Note 10: For example, if C
B
= 300pF, then t
R
[min] = t
F
[min] = 50ns.
Note 11: This timeout applies only when the DS75LX is holding SDA low. Other devices can hold SDA low indefinitely and the DS75LX
will not reset.
Note 12: The DS75LX is available with timeout feature disabled upon special order. Contact Factory.
PIN DESCRIPTION
PIN NAME FUNCTION
1 SDA Data Input/Output for 2-Wire Serial Communication Port (Open Drain)
2 SCL Clock Input for 2-Wire Serial Communication Port
3 O.S. Thermostat Output Open Drain
4 GND Ground
5 A
2
Address Input
6 A
1
Address Input
7 A
0
Address Input
8 V
DD
Supply Voltage. +1.7V to +3.7V supply pin. V
DD
must have an external bypass
capacitor to GND. 0.1µF X5R or X7R ceramic SMT caps recommended.