Datasheet

(1.7V ≤ V
DD
≤ 3.7V, T
A
= -55°C to +125°C, unless otherwise noted.)
Note 1: The DS75LV has a maximum operating voltage of 3.7V. Contact the factory for information on the availability of a 3.7V to
5.5V version of the DS75LV.
Note 2: Internal heating caused by OS loading causes the DS75LV to read approximately 0.5°C higher if OS is sinking the max
rated current.
Note 3: All voltages are referenced to ground.
Note 4: I
DD
specified with V
DD
at 3.0V and SDA, SCL = 3.0V, 0°C to +70°C.
Note 5: I
DD
specified with OS pin open.
Note 6: See Figure 2 for timing diagram. All timing is referenced to 0.9 x V
DD
and 0.1 x V
DD
.
Note 7: After this period, the first clock pulse is generated.
Note 8: The DS75LV provides an internal hold time of at least 75ns on the SDA signal to bridge the undefined region of SCL’s fall-
ing edge.
Note 9: For example, if C
B
= 300pF, then t
RMIN
= t
FMIN
= 50ns.
Note 10: This timeout applies only when the DS75LV is holding SDA low. Other devices can hold SDA low indefinitely and the
DS75LV does not reset.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Low Period of SCL t
LOW
(Note 6) 1.3 µs
High Period of SCL t
HIGH
(Note 6) 0.6 µs
Repeated START Condition
Setup Time to Rising SCL
t
SU:STA
(Note 6) 600 ns
Data-Out Hold Time from
Falling SCL
t
HD:DAT
(Notes 6, 8) 0 0.9 µs
Data-In Setup Time to Rising
SCL
t
SU:DAT
(Note 6) 100 ns
Rise Time of SDA and SCL
(Receive)
t
R
(Notes 6, 9) 20 + 0.1C
B
300 ns
Fall Time of SDA and SCL
(Receive)
t
F
(Notes 6, 9) 20 + 0.1C
B
300 ns
Spike Suppression Filter Time
(Deglitch Filter)
t
SS
0 50 ns
STOP Setup Time to Rising
SCL
t
SU:STO
(Note 6) 600 ns
Capacitive Load for Each Bus
Line
C
B
400 pF
Input Capacitance C
I
5 pF
Serial Interface Reset Time t
TIMEOUT
SDA time low (Note 10) 75 325 ms
DS75LV Digital Thermometer and Thermostat
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AC Electrical Characteristics (continued)