Datasheet

DS5002FP Secure Microprocessor Chip
8 of 25
AC CHARACTERISTICS—BYTE-WIDE ADDRESS/DATA BUS TIMING
(V
CC
= 5V ±10%, T
A
= 0°C to +70°C.) (Figure 6)
# PARAMETER SYMBOL MIN MAX UNITS
40
Delay to Byte-Wide Address Valid from
CE1,
CE2, or CE1N Low During Op Code Fetch
t
CE1LPA
30 ns
41
Pulse Width of
CE1–4, PE1–4, or CE1N
t
CEPW
4t
CLK
- 35 ns
42
Byte-Wide Address Hold After
CE1, CE2, or
CE1N High During Op Code Fetch
t
CE1HPA
2t
CLK
- 20 ns
43
Byte-Wide Data Setup to
CE1, CE2, or CE1N
High During Op Code Fetch
t
OVCE1H
1t
CLK
+ 40 ns
44
Byte-Wide Data Hold After
CE1, CE2, or CE1N
High During Op Code Fetch
t
CE1HOV
0 ns
45
Byte-Wide Address Hold After
CE1–4, PE1–4, or
CE1N High During MOVX
t
CEHDA
4t
CLK
- 30 ns
46
Delay from Byte-Wide Address Valid
CE1–4,
PE1–4, or CE1N Low During MOVX
t
CELDA
4t
CLK
- 35 ns
47
Byte-Wide Data Setup to
CE1–4, PE1–4, or
CE1N High During MOVX (Read)
t
DACEH
1t
CLK
+ 40 ns
48
Byte-Wide Data Hold After
CE1–4, PE1–4, or
CE1N High During MOVX (Read)
t
CEHDV
0 ns
49
Byte-Wide Address Valid to R/
W Active During
MOVX (Write)
t
AVRWL
3t
CLK
- 35 ns
50
Delay from R/
W Low to Valid Data Out During
MOVX (Write)
t
RWLDV
20 ns
51
Valid Data Out Hold Time from
CE1–4, PE1–4, or
CE1N High
t
CEHDV
1t
CLK
- 15 ns
52
Valid Data Out Hold Time from R/
W High
t
RWHDV
0 ns
53
Write Pulse Width (R/
W Low Time)
t
RWLPW
6t
CLK
- 20 ns
Figure 6. Byte-Wide Bus Timing