Datasheet

DS5002FP Secure Microprocessor Chip
4 of 25
AC CHARACTERISTICS—EXPANDED BUS MODE TIMING SPECIFICATIONS
(V
CC
= 5V ±10%, T
A
= 0°C to +70°C.) (Figure 1 and Figure 2)
# PARAMETER SYMBOL CONDITIONS MIN MAX UNITS
1 Oscillator Frequency 1 / t
CLK
1.0 16 MHz
2 ALE Pulse Width t
ALPW
2t
CLK
- 40 ns
3 Address Valid to ALE Low t
AVALL
t
CLK
- 40 ns
4 Address Hold After ALE Low t
AVAAV
t
CLK
- 35 ns
14
RD Pulse Width
t
RDPW
6t
CLK
- 100 ns
15
WR Pulse Width
t
WRPW
6t
CLK
- 100 ns
12MHz 5t
CLK
- 165
16
RD Low to Valid Data In
t
RDLDV
16MHz 5t
CLK
- 105
ns
17
Data Hold after
RD High
t
RDHDV
0 ns
18
Data Float after
RD High
t
RDHDZ
2t
CLK
- 70 ns
12MHz 8t
CLK
- 150
19 ALE Low to Valid Data In t
ALLVD
16MHz 8t
CLK
- 90
ns
12MHz 9t
CLK
- 165
20 Valid Address to Valid Data In t
AVDV
16MHz 9t
CLK
- 105
ns
21
ALE Low to
RD or WR Low
t
ALLRDL
3t
CLK
- 50 3t
CLK
+ 50 ns
22
Address Valid to
RD or WR
Low
t
AVRDL
4t
CLK
- 130 ns
23
Data Valid to
WR Going Low
t
DVWRL
t
CLK
- 60 ns
12MHz 7t
CLK
- 150
24
Data Valid to
WR High
t
DVWRH
16MHz 7t
CLK
- 90
ns
25
Data Valid after
WR High
t
WRHDV
t
CLK
-50 ns
26
RD Low to Address Float
t
RDLAZ
0 ns
27
RD or WR High to ALE High
t
RDHALH
t
CLK
- 40 t
CLK
+ 50 ns
Figure 1. Expanded Data Memory Read Cycle