Datasheet

DS4M125/DS4M133/DS4M200
3.3V Margining Clock Oscillator with
LVPECL/LVDS Output
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 3.135V to 3.465V, T
A
= -40°C to +85°C, unless otherwise noted.) (Notes 1, 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input-Voltage Low (OE) V
IL
(Note 5) 0
0.3 x
V
CC
V
Input-Leakage High (OE) I
LEAKH
OE voltage = VCC -5 +5 μA
Input-Leakage Low (OE) I
LEAKL
OE voltage = GND -20 -50 μA
Input-Leakage High (MS) I
LEAKH
MS voltage = VCC 20 50 μA
Input-Leakage Low (MS) I
LEAKL
MS voltage = GND -5 +5 μA
Input Voltage: High Level (MS) V
IH
(Note 5)
0.75 x
V
CC
+
0.15V
V
CC
V
Input Voltage: Mid Level (MS) V
IM
(Note 5)
0.25 x
V
CC
+
0.15V
0.75 x
V
CC
-
0.15V
V
Input Voltage: Low Level (MS) V
IL
(Note 5) 0
0.25 x
V
CC
-
0.15V
V
LVDS
Output High Voltage V
OH
100 differential load (Notes 2, 5) 1.475 V
Output Low Voltage V
OL
100 differential load (Notes 2, 5) 0.925 V
Differential Output Voltage
|
V
OD
|
100 differential load 250 425 mV
Change in V
OD
for
Complementary States

|
V
OD
|
100 differential load 25 mV
Offset Output Voltage V
OS
100 differential load (Note 2) 1.125 1.275 V
Change in V
OS
for
Complementary States

|
V
OS
|
100 differential load 150 mV
Differential Output Impedance R
OLVDS
80 140 
L
VSSLVDSO
OUTN or OUTP shorted to ground and
measure the current in the shorting path
40
Output Current
L
LVDSO
OUTN and OUTP shorted together and
measure the change in I
CC
6.5
mA
Output Rise Time (Differential) t
RLVDSO
20% to 80% 175 ps
Output Fall Time (Differential) t
FLVDSO
80% to 20% 175 ps
Duty Cycle D
CYCLE_LVDS
45 55 %
Propagation Delay from OE Going
LOW to Logical 1 at OUTP
t
PA1
(Figure 2) 200 ns
Propagation Delay from OE Going
HIGH to Output Active
t
P1A
(Figure 2) 200 ns