Datasheet
DS4830
Optical Microcontroller
8Maxim Integrated
SPI DIGITAL INTERFACE SPECIFICATION (continued)
(V
DD
= 2.97V to 3.63V, T
A
= -40NC to +85NC, unless otherwise noted.) (See Figure 3 and Figure 4.)
ELECTRICAL CHARACTERISTICS: JTAG INTERFACE
(V
DD
= 2.97V to 3.63V, T
A
= -40NC to +85NC, unless otherwise noted.) (Figure 5)
Note 1: All voltages are referenced to GND. Currents entering the IC are specified as positive, and currents exiting the IC are
specified as negative.
Note 2: Maximum current assuming 100% CPU duty cycle.
Note 3: This value does not include current in GPIO, SCL, SDA, MDIO, MDI, MCL, REFINA, and REFINB.
Note 4: Using internal reference.
Note 5: There is one internal oscillator. The oscillator (peripheral clock) goes through a 2:1 divider to create the core clock.
Note 6: Guaranteed by design.
Note 7: ADC conversions are delayed up to 1.6Fs if the fast comparator is sampling the selected ADC channel. This can cause a
slight decrease in the ADC sampling rate.
Note 8: Temperature readings average 64 times.
Note 9: Programming time does not include overhead associated with the utility ROM interface.
Note 10: f
SCL
must meet the minimum clock low time plus the rise/fall times.
Note 11: This device internally provides a hold time of at least 75ns for the SDA signal (referred to the V
IH:MIN
of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 12: C
B
—Total capacitance of one bus line in pF.
Note 13: Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SSPIDO Output Valid After
SSPICK Shift Edge Transition
t
SOV
2t
SPI_RF
ns
SSPICS Inactive t
SSH
t
SSPICK
+
t
SPI_RF
ns
SSPICK Inactive to SSPICS
Rising
t
SD
t
SPI_RF
ns
SSPIDO Output Disabled After
SSPICS Edge Rise
t
SLH
2t
SSPICK
+
2t
SPI_RF
ns
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
JTAG Logic Reference V
REF
V
DD
/2 V
TCK High Time t
TH
0.5 Fs
TCK Low Time t
TL
0.5 Fs
TCK Low to TDO Output t
TLQ
0.125 Fs
TMS, TDI Input Setup to TCK High t
DVTH
0.25 Fs
TMS, TDI Input Hold After TCK
High
t
THDX
0.25 Fs