Datasheet

DS4830
Optical Microcontroller
7Maxim Integrated
3-WIRE DIGITAL INTERFACE SPECIFICATION
(V
DD
= 2.97V to 3.63V, T
A
= -40NC to +85NC, unless otherwise noted.) (See Figure 2.)
SPI DIGITAL INTERFACE SPECIFICATION
(V
DD
= 2.97V to 3.63V, T
A
= -40NC to +85NC, unless otherwise noted.) (See Figure 3 and Figure 4.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
MCL Clock Frequency f
SCLOUT
1000 kHz
MCL Duty Cycle t
3WDC
50 %
MDIO Setup Time t
DS
100 ns
MDIO Hold Time t
DH
100 ns
MCS Pulse-Width Low t
CSW
500 ns
MCS Leading Time Before the
First MCL Edge
t
L
500 ns
MCS Trailing Time After the Last
MCL Edge
t
T
500 ns
MDIO, MCL Load C
B3W
Total bus capacitance on one line 10 pF
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SPI Master Operating Frequency 1/t
MSPICK
f
SYS
/2 MHz
SPI Slave Operating Frequency 1/t
SSPICK
f
SYS
/4 MHz
SPI I/O Rise/Fall Time t
SPI_RF
C
L
= 15pF, pullup = 560I 25 ns
MSPICK Output Pulse-Width
High/Low
t
MCH, tMCL
t
MSPICK
/2
- t
SPI_RF
ns
MSPIDO Output Hold After
MSPICK Sample Edge
t
MOH
t
MSPICK
/2
- t
SPI_RF
ns
MSPIDO Output Valid to
MSPICK Sample Edge (MSPIDO
Setup)
t
MOV
t
MSPICK
/2
- t
SPI_RF
ns
MSPIDI Input Valid to MSPICK
Sample Edge (MSPIDI Setup)
t
MIS
2t
SPI_RF
ns
MSPIDI Input to MSPICK Sample
Edge Rise/Fall Hold
t
MIH
0 ns
MSPICK Inactive to MSPIDO
Inactive
t
MLH
t
MSPICK
/2
- t
SPI_RF
ns
SSPICK Input Pulse-Width High/
Low
t
SCH
, t
SCL
t
SSPICK
/2 ns
SSPICS Active to First Shift
Edge
t
SSE
t
SPI_RF
ns
SSPIDI Input to SSPICK Sample
Edge Rise/Fall Setup
t
SIS
t
SPI_RF
ns
SSPIDI Input from SSPICK
Sample Edge Transition Hold
t
SIH
t
SPI_RF
ns