Datasheet

DS4830
Optical Microcontroller
23Maxim Integrated
contains six peripheral modules, M0 to M5. An MIIR reg-
ister is implemented in modules M1 and M2. The MIIRs
are 16-bit read-only registers and all of them default to
all zeros on system reset. Once the module that causes
the interrupt is singled out, it can then be interrogated
for the specific interrupt source and software can take
appropriate action. Interrupts are evaluated by applica-
tion code allowing the definition of a unique interrupt
priority scheme for each application. Interrupt sources
are available from the watchdog timer, the ADC (includ-
ing sample/holds), fast comparators, the programmable
timer, SVM, the I
2
C-compatible master and slave inter-
face, 3-wire, master and slave SPI, and all GPIO pins.
I/O Port
The device allows for most inputs and outputs to function
as general-purpose input and/or output pins. There are
four ports: P0, P1, P2, and P6. Note that there is no port
corresponding to P6.7. The 7th bit of port 6 is nonfunc-
tional in all SFRs. Each pin is multiplexed with at least one
special function, such as interrupts, I/O pins, or JTAG
pins, etc.
The GPIO pins have Schmitt trigger receivers and full
CMOS output drivers and can support alternate functions.
The ports can be accessed through SFRs (PO[0,1,2,6],
PI[0,1,2,6], PD[0,1,2,6], EIE[0,1,2,6], EIF[0,1,2,6], and
EIES[0,1,2,6]) in modules 0 and 1, and each pin can be
individually configured. The pin is either high impedance
or a weak pullup when defined as an input, dependent on
the state of the corresponding bit in the output register. In
addition, each pin can function as external interrupt with
individual enable, flag and active edge selection, when
programmed as input.
The I/O port SFRs are accessed in module 0 and 1.
Detailed information regarding the GPIO block can be
found in the DS4830 User’s Guide.
DAC Outputs
The device provides eight 12-bit DAC outputs with multi-
ple reference options. An internal 2.5V reference is pro-
vided. There are also two selectable external references.
REFINA can be selected as the full-scale reference for
DAC0 to DAC3. REFINB can be selected as the full-scale
reference for DAC4 to DAC7. The DAC outputs are volt-
age buffered. Each DAC can be individually disabled and
put into a low-power power-down mode using DACCFG.
An external reset does not affect the DAC outputs.
If a DAC output is used during the lifetime of the DS4830,
the DAC must always be enabled to guarantee meeting
the INL and offset specifications. If a pin is used for a
DAC, it should be used only for the DAC function. The
pin’s function should not be switched between DAC and
PWM or switched between DAC and GPIO.
The DAC SFRs are accessed in module 4. Detailed
information regarding the DAC block can be found in the
DS4830 User’s Guide.
PWM Outputs
The device provides 10 independently configurable
PWM outputs. The PWM outputs are configured using
three SFRs: PWMCN, PWMDATA, and PWNSYNC. Using
PWMCN and PWMDATA, individual PWM channels can
be programmed for unique duty cycles (DCYCn), con-
figurations (PWMCFGn), and delays (PWMDLYn), where
n represents the PWM channel number.
The PWM clock can be obtained from the core clock,
peripheral clock, or an external clock, depending on
CLK_SEL bits programmed in individual PWMCFGn reg-
isters. The PWMCFGn register also enables/disables the
corresponding PWM output and selects the PWM polar-
ity. The user can set the duty cycle and the frequency
of each PWM output individually by configuring the cor-
responding DCYCn register and the PWMCFGn register.
The device allows 4-slot or 32-slot pulse spreading
options for each PWM channel. The PWM outputs can be
configured to be output on an alternate location using the
configuration register. PWMDLY is a 12-bit register used
for providing starting delay on different PWM channels,
and can be used to create multiphase PWM operation.
Different channels can be synchronized using the
PWMSYNC register. Doing so effectively brings the
channels in phase by restarting the channels that are to
be synchronized. An external reset does not affect the
PWM outputs.
The PWM SFRs are accessed in module 5. Detailed
information regarding the PWM block can be found in the
DS4830 User’s Guide.