Datasheet

DS4830
Optical Microcontroller
18Maxim Integrated
Detailed Description
The following is an introduction to the primary features
of the DS4830 optical microcontroller. More detailed
descriptions of the device features can be found in the
DS4830 User’s Guide.
Microcontroller Core Architecture
The device employs a low-power, low-cost, high-perfor-
mance, 16-bit RISC microcontroller with on-chip flash
memory. It is structured on an advanced, 16 accumula-
tor-based, 16-bit RISC architecture. Fetch and execution
operations are completed in one cycle without pipelining,
since the instruction contains both the op code and data.
The highly efficient core is supported by 16 accumulators
and a 16-level hardware stack, enabling fast subroutine
calling and task switching. Data can be quickly and
efficiently manipulated with three internal data pointers.
Multiple data pointers allow more than one function to
access data memory without having to save and restore
data pointers each time. The data pointers can auto-
matically increment or decrement following an operation,
eliminating the need for software intervention.
Module Information
Top-level instruction decoding is extremely simple and
based on transfers to and from registers. The registers
are organized into functional modules, which are in turn
divided into the system register and peripheral register
groups.
Peripherals and other features are accessed through
peripheral registers. These registers reside in modules
0 to 5. The following provides information about the spe-
cific module in which each peripheral resides:
• Module 0: Timer 1, GPIO Ports 0, 1, and 2
• Module 1: I
2
C Master, GPIO Port 6, SPI Slave, SVM
• Module 2: I
2
C Slave, Analog-to-Digital Converter
(ADC), Sample/Hold, Temperature, 3-Wire Master
• Module 3: Timer 2, MAC-Related Registers
• Module 4: Digital-to-Analog Converter (DAC)
• Module 5: Quick Trips, SPI Master, PWM
Instruction Set
The instruction set is composed of fixed-length, 16-bit
instructions that operate on registers and memory loca-
tions. The instruction set is highly orthogonal, allowing
arithmetic and logical operations to use any register
along with the accumulator. Special-function registers
control the peripherals and are subdivided into register
modules.
Memory Organization
The device incorporates several memory areas:
• 32 kWords of flash memory for application program
storage
• 1kWordsofSRAMforstorageoftemporaryvariables
• 4kWordsofutilityROMcontainadebuggerandpro-
gram loader
• 16-levelstackmemoryforstorageofprogramreturn
addresses and general-purpose use
The memory is implemented with separate address
spaces for program memory, data memory, and register
space. ROM, application code, and data memory can be
placed into a single contiguous memory map. The device
allows data memory to be mapped into program space,
permitting code execution from data memory. In addition,
program memory can be mapped into data space, per-
mitting code constants to be accessed as data memory.
Figure 6 shows the DS4830’s memory map when execut-
ing from program memory space. Refer to the DS4830
User’s Guide for memory map information when execut-
ing from data or ROM space.
The incorporation of flash memory allows field upgrade of
the firmware. Flash memory can be password protected
with a 16-word key, denying access to program memory
by unauthorized individuals.
Utility ROM
The utility ROM is a 4 kWord block of internal ROM
memory that defaults to a starting address of 8000h. The
utility ROM consists of subroutines that can be called
from application software, which includes the following:
• In-systemprogramming(bootstraploader)overJTAG
or I
2
C-compatible interfaces
• In-circuitdebugroutines