User guide

DS4830A User’s Guide
40
SECTION 5 – INTERRUPTS
The DS4830A provides a single, programmable interrupt vector (IV) that can be used to handle internal and external
interrupts. Interrupts can be generated from system level sources (e.g., watchdog timer) or by sources associated
with the peripheral modules. Only one interrupt can be handled at a time, and all interrupts naturally have the same
priority. A programmable interrupt mask register allows software-controlled prioritization and nesting of high-priority
interrupts. igure 5-1 shows a diagram of the interrupt hierarchy.
System Module
WATCHDOG INTERRUPT
WDCN.WDIF
WDCN.EWDI
(local enable
)
IMR.IMS
Module Enable
Module 0
GPIO INTERRUPTS
External Interrupt Pn.: EIFn.IFPn_m
Local Enable EIEn.IEPn_m
n can be 0,1 or 2 and m can be 0
to 7
TIMER1 INTERRUPT
Timer1
Flag GTIF
Timer Local Enable GTIE
IMR.IM0
Module0 Enable
IIR
.IIS
IIR.II0
Module 3
IMR.IM
3
Module3 Enable
IIR.II3
TIMER2 INTERRUPT
Timer Local Enable GTIE
External Interrupt P
2
.0
: EIF
2
.IFP
2_
0
Local Enable EIE2
.IEP2_0
Timer2
Flag GTIF
Note: Only a few of the DS4830A modules and interrupt sources are shown in this interrupt hierarchy
figure. Please refer to the corresponding sections of this user’s guide for more detailed information
about all of the possible interrupts.
Module 1
External Interrupt P6.
m: EIF
6.IFP6
_m
Local Enable EIE
6.IEP6_m
m can be 0 to 6
PORT6 GPIO INTERRUPTS
Master I
2
C START Interrupt
I2
CST_M
.I2CSRI
Local Enable I
2CIE_
M.I
2CSRIE
Any I
2
C Interrupt I
2CST_M.x
Local Enable I2CIE
_M.
x
SVM Interrupt SVM
.SVMI
Local Enable SVM.SVMIE
MASTER I
2
C INTERRUPTS
SVM INTERRUPT
Module1 Enable
IIR.
III1
JUMP TO
INTERRUPT
VECTOR
IC.INS
Interrupt is NOT
in Service
IC.IGE
Global Enable
IMR
.IM1
SW Interrupt flag
Figure 5-1: Interrupt Hierarchy