User guide

DS4830A User’s Guide
163
commands and data can be exchanged between the host and the DS4830A by operating in the data register portion
of the state sequence (i.e. DR-Scan). The TAP retains the private instruction which was loaded into IR2:0 until a new
instruction is shifted in or until the TAP controller returns to the Test-Logic-Reset state.
20.3.1 – TAP Communication Examples – IR-Scan and DR-Scan
Figures 20-3 and 20-4 illustrate examples of communication between the host JTAG controller and the Test Access
Port (TAP) of the DS4830A. The host controls the TCK and TMS signals to move through the desired TAP states
while accessing the selected shift register through the TDI input and TDO output pair.
Run-
Test/I
dle
Up
d
a
t
e
-
I
R
E
xit
1-IR
P
aus
e-I
R
Ex
it2-
IR
Shi
ft-
IR
Ex
it1-
IR
Selec
t-DR-S
can
New Instruction
Instruction Register
Test-Lo
gic-Re
set
TCK
TMS
TDI
TDO
Control
State
IR Shift
Register
IR Parallel
Output
Register
Selected
TDO
Enable
Captu
re-I
R
S
hi
ft
-IR
S
elect-I
R-Scan
Ru
n-
T
es
t/
I
dl
e
By-Pass
Don’t care or undefinedDon’t care or undefined
Don’t care or undefined Don’t care or undefined
Figure 20-3: TAP Controller Debug Mode IR-Scan Example