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DS4830A

Optical Microcontroller

User’s Guide

Rev 0; 12/13

Summary of content (240 pages)

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DS4830A Optical Microcontroller User’s Guide Rev 0; 12/13 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, Inc.
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DS4830A User’s Guide Contents SECTION 1 – OVERVIEW .................................................................................................................................................... 11 SECTION 2 – ARCHITECTURE ........................................................................................................................................... 13 2.1 – Instruction Decoding .................................................................................................................
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DS4830A User’s Guide 3.18 – General Register (GR, 0Eh[05h]) ........................................................................................................................... 31 3.19 – General Register Low Byte (GRL, 0Eh[06h]) ......................................................................................................... 31 3.20 – Frame Pointer Base Register (BP, 0Eh[07h]) ........................................................................................................ 31 3.
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DS4830A User’s Guide 7.1.10 – ADC Data Reading .......................................................................................................................................... 54 7.1.11 – ADC Interrupts ................................................................................................................................................. 54 7.1.12 – ADC Internal Offset .........................................................................................................................
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DS4830A User’s Guide 10.1.7 – Transmitting a Slave Address .......................................................................................................................... 85 10.1.8 – Transmitting Data............................................................................................................................................. 85 10.1.9 – Receiving Data.....................................................................................................................................
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DS4830A User’s Guide SECTION 13 – 3-WIRE....................................................................................................................................................... 121 13.1 – Detailed Description ............................................................................................................................................. 121 13.1.1 – Operation ...........................................................................................................................
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DS4830A User’s Guide 18.4.1 – Accessing the Multiplier ................................................................................................................................. 149 18.5 – Hardware Multiplier Peripheral Registers ............................................................................................................. 151 18.6 – Hardware Multiplier Examples .............................................................................................................................
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DS4830A User’s Guide 22.3.4 – Command 03h – Password Match................................................................................................................. 185 22.3.5 – Command 04h – Get Status .......................................................................................................................... 185 22.3.6 – Command 05h – Get Supported Commands ................................................................................................ 186 22.3.
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DS4830A User’s Guide 23.7.2 – Unconditional Jumps ..................................................................................................................................... 197 23.7.3 – Conditional Jumps ......................................................................................................................................... 198 23.7.4 – Calling Subroutines ..............................................................................................................................
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DS4830A User’s Guide 26.5 – Device Number and I2C Bootloader Address Disable .......................................................................................... 240 26.5.1 – Device Number Register (DEV_NUM)...........................................................................................................
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DS4830A User’s Guide SECTION 1 – OVERVIEW The DS4830A optical microcontroller is a low-power, 16-bit microcontroller with a unique peripheral set supporting a wide variety of optical transceiver controller applications. It provides a complete optical control, calibration, and monitor solution. The DS4830A is based on the high-performance, 16-bit, reduced instruction set computing (RISC) architecture with on-chip flash program memory and SRAM data memory.
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DS4830A User’s Guide Figure 1-1: DS4830A Block Diagram This document is provided as a supplement to the DS4830A IC data sheet. This user’s guide provides the information necessary to develop applications using the DS4830A. All electrical and timing specifications, pin descriptions, package information, and ordering information can be found in the DS4830A IC data sheet.
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DS4830A User’s Guide SECTION 2 – ARCHITECTURE The DS4830A contains a low-cost, high-performance microcontroller with flash memory. It is structured on a highly advanced, 16-accumulator-based, 16-bit RISC architecture. Fetch and execution operations are completed in one cycle without pipelining, since the instruction contains both the opcode and data. The highly efficient core is supported by 16 accumulators and a 32-level hardware stack, enabling fast subroutine calling and task switching.
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DS4830A User’s Guide done automatically by the assembler and requires one additional execution cycle. So, while most instructions execute in a single cycle, two cycles are needed for instructions that require the prefix register. The architecture of the DS4830A is transport-triggered. This means that writing to or reading from certain register locations will also cause side effects to occur. These side effects form the basis of the DS4830A’s higher level opcodes, such as ADDC, OR, and JUMP.
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DS4830A User’s Guide the source data will be equal to the prefix data as the upper 8 bits and 00h as the lower 8 bits. If the source is from a module containing only 16-bit source registers, 0000h source data is used for the transfer. Table 2-1.
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DS4830A User’s Guide 2.3.4 – Stack Memory A 16-bit, 32-level on-chip stack provides storage for program return addresses and temporary storage of system registers. The stack is used automatically by the processor when the CALL, RET, and RETI instructions are executed, and when an interrupt is serviced. The stack can also be used explicitly to store and retrieve data by using the @SP- - source, @++SP destination, or the PUSH, POP, and POPI instructions.
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DS4830A User’s Guide 2.4.2 – Program Memory Mapping The DS4830A’s mapping of the three memory segments (flash, SRAM, and utility ROM) as program memory is shown in Figure 2-2. The mapping of memory segments into program space is always the same. When referring to memory as program memory, all addresses are given as word addresses. The 32KWord flash memory segment is located at memory location 0000h through 7FFFh and is logically divided into two pages, each containing 16KWords.
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DS4830A User’s Guide pointer. If the data pointer is used as destination, the core performs a store operation that writes data to the memory location addressed by the data pointer. Following are some examples of setting and using a data pointer. move DP[0], #0100h move Acc, @DP[0] move @DP[0], Acc ; set pointer DP[0] to address 100h ; read data from location 100h ; write to location 100h The address pointed to by the data pointers can be automatically incremented or decremented.
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DS4830A User’s Guide 2.4.4.1 – Memory Map When Executing from Flash Memory When executing from the flash memory: • Read and write operations of SRAM memory are executed normally. • The utility ROM can be read as data, starting at 8000h of the data space. The utility ROM cannot be written. Figure 2-3 illustrates the mapping of the SRAM and utility ROM memory segments into data memory space when code is executing from the flash memory segment.
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DS4830A User’s Guide 2.4.4.2 – Memory Map When Executing from Utility ROM When executing from the utility ROM: • Read and write operations of SRAM memory are executed normally. • Reading of flash memory is executed normally. Writing to flash memory requires the use of the utility ROM routines. • One page (byte access mode) or both pages (word access mode) of the flash memory can be accessed as data with an offset of 8000h as determined by the CDA0 bit.
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DS4830A User’s Guide 2.4.4.3 – Memory Map When Executing from SRAM When executing from the SRAM: • The utility ROM can be read as data, starting at 8000h of the data space. The utility ROM cannot be written. • Reading of flash memory is executed normally. Writing to flash memory requires the use of the utility ROM routines. • One page (byte access mode) or both pages (word access mode) of the flash memory can be accessed as data with an offset of 0000h.
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DS4830A User’s Guide 2.5 – Data Alignment To support merged program and data memory operation while maintaining efficient memory space usage, the data memory must be able to support both byte and word mode accessing. Data is aligned in data memory as words, but the effective data address is resolved to bytes. This data alignment allows program instruction fetching in words while maintaining data accessibility at the byte level.
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DS4830A User’s Guide POR BROWNOUT STATE CPU DISABLED ANALOG ACTIVE VDD > VBO VDD < VBO SYSTEM CLOCK STARTUP DELAY CPU MODE VDD < VBO DIGITAL CORE ON ANALOG ON CODE EXECUTION Figure 2-6: DS4830A State Diagram 2.6.2 – Watchdog Timer Reset The watchdog timer is a programmable hardware timer that can be used to reset the processor in case a software lockup or other unrecoverable error occurs. Once the watchdog is enabled, software must reset the watchdog timer periodically.
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DS4830A User’s Guide 2.6.4 – Internal System Resets There are two possible sources of internal system resets. An internal reset will hold the DS4830A in reset mode for 12 clock cycles. 1. When data BBh is written to the special I2C slave address 34h. 2. When in-system programming is complete and the ROD bit is set to 1. 2.6.5 – Software Reset The device UROM provides option to soft reset through the application program. The application program jumps to UROM code which generates the internal system reset.
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DS4830A User’s Guide SECTION 3 – SYSTEM REGISTER DESCRIPTIONS Most functions of the DS4830A are controlled by sets of registers. These registers provide a working space for memory operations as well as configuring and addressing peripheral registers on the device. Registers are divided into two major types: system registers and peripheral registers.
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DS4830A User’s Guide Table 3-2.
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DS4830A User’s Guide 3.1 – Accumulator Pointer Register (AP, 08h[00h]) Initialization: This register is cleared to 00h on all forms of reset. Access: Unrestricted direct read/write access. Bit Name Function 7:4 Reserved Reserved. All reads return 0. Active Accumulator Select. These bits select which of the 16 accumulator registers are used for arithmetic and logical operations.
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DS4830A User’s Guide 3.4 – Interrupt and Control Register (IC, 08h[05h]) Initialization: This register is cleared to 00h on all forms of reset. Access: Unrestricted direct read/write access. Bit Name Function 7:2 Reserved Reserved. All reads return 0. Interrupt In Service. The INS is set by hardware automatically when an interrupt is acknowledged. No further interrupts occur as long as the INS remains set. The interrupt service routine can clear the INS 1 INS bit to allow interrupt nesting.
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DS4830A User’s Guide 3.7 – Interrupt Identification Register (IIR, 08h[0Bh]) Initialization: This register is cleared to 00h on all forms of reset. Access: Read only. Bit Name Function 7 IIS Interrupt Identifier Flag for System Modules 6 Reserved Reserved. All reads return 0.
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DS4830A User’s Guide 3.11 – Instruction Pointer Register (IP, 0Ch[00h]) Initialization: This register is cleared to 8000h on all forms of reset. Access: Unrestricted direct read/write access. BIT DESCRIPTION This register contains the address of the next instruction to be executed and is automatically 15:0 incremented by 1 after each program fetch. Writing an address value to this register will cause program flow to jump to that address. Reading from this register will not affect program flow. 3.
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DS4830A User’s Guide 3.17 – Data Pointer Control Register (DPC, 0Eh[04h]) Initialization: This register is cleared to 001Ch on all forms of reset. Access: Unrestricted direct read/write access. BIT NAME DESCRIPTION 15:5 RESERVED Reserved. All reads return 0. Word/Byte Select 2. This bit selects access mode for BP[OFFS]. When WBS2 is set to logic 1, the 4 WBS2 BP[Offs] is operated in word mode for data memory access; when WBS2 is cleared to logic 0, BP[Offs] is operated in byte mode for data memory access.
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DS4830A User’s Guide 3.21 – General Register Byte-Swapped (GRS, 0Eh[08h]) Initialization: This register is cleared to 0000h on all forms of reset Access: Unrestricted read-only access. BIT DESCRIPTION This register is intended primarily for supporting byte operations on 16-bit data. This 16-bit read 15:0 only register returns the byte-swapped value for the data contained in the GR register. 3.
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DS4830A User’s Guide SECTION 4 – PERIPHERAL REGISTER DESCRIPTIONS Reg M0 M1 M2 M3 M4 M5 0 PO2 I2CBUF_M I2CBUF_S MCNT ADCN QTDATA 1 PO1 I2CST_M I2CST_S MA SENR QTCN 2 PO0 I2CIE_M MPNTR MB ADST LTIL 3 EIF2 PO6 I2CTXFST MC2 ADST1 HTIL 4 EIF1 CRC8IN I2CTXFIE MC1 ADDATA SPIB_M 5 EIF0 MIIR1 I2CRXFST MC0 SPIB_S PWMDATA 6 GTV1 EIF6 I2CRXFIE GTCN2 DADDR PWMCN 7 GTCN1 EIE6 I2CST2_S SHFT MIIR4 PWMSYNC 8 PI2 PI6 RPNTR MC1R TEMPCN LTIH 9 PI1 SVM I
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DS4830A User’s Guide 4.
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DS4830A User’s Guide SECTION 5 – INTERRUPTS The DS4830A provides a single, programmable interrupt vector (IV) that can be used to handle internal and external interrupts. Interrupts can be generated from system level sources (e.g., watchdog timer) or by sources associated with the peripheral modules. Only one interrupt can be handled at a time, and all interrupts naturally have the same priority.
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DS4830A User’s Guide Note: Some of the DS4830A module and peripheral interrupts sources are shown in the Figure 5-1 interrupt hierarchy diagram. See the corresponding sections of this user’s guide for more detailed information about all of the possible interrupts. 5.1 – Servicing Interrupts For the DS4830A to service an interrupt, interrupts must be enabled locally, modularly, and globally.
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DS4830A User’s Guide INTERRUPT LT 0 Interrupt LT 1 Interrupt LT 2 Interrupt LT 3 Interrupt LT 4 Interrupt LT 5 Interrupt LT 6 Interrupt LT 7 Interrupt LT 8 Interrupt LT 9 Interrupt LT 10 Interrupt LT 11 Interrupt LT 12 Interrupt LT 13 Interrupt LT 14 Interrupt LT 15 Interrupt HT 0 Interrupt HT 1 Interrupt HT 2 Interrupt HT 3 Interrupt HT 4 Interrupt HT 5 Interrupt HT 6 Interrupt HT 7 Interrupt HT 8 Interrupt HT 9 Interrupt HT 10 Interrupt HT 11 Interrupt HT 12 Interrupt HT 13 Interrupt HT 14 Interrupt HT 15
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DS4830A User’s Guide enable bits and combined to create a single interrupt identification bit for that specific function. For example, the I2C master has several interrupt sources; however, they all are combined to form a single identification bit, MIIR1.I2CM. The individual register bit functions are defined as follows.
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DS4830A User’s Guide 1. 2. 3. 4. The next instruction fetch from program memory is cancelled. The return address is pushed on to the stack. The INS bit is set to 1 to prevent recursive interrupt calls. The instruction pointer is set to the location of the interrupt service routine (contained in the Interrupt Vector register). 5. The CPU begins executing the interrupt service routine. Once the interrupt service routine completes, it should use the RETI instruction to return to the main program.
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DS4830A User’s Guide SECTION 6 – DIGITAL-TO-ANALOG CONVERTER (DAC) The DS4830A contains eight 12-bit digital-to-analog converters (DACs). Each DAC has a voltage output buffer. Each DAC can independently select between a 2.5V internal reference and external reference at REFINA pin for DAC0 to DAC3 and at REFINB pin for DAC4 to DAC7.
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DS4830A User’s Guide DS4830A IC data sheet). The DAC output voltage is maintained during any type of reset except POR. All DACs, REFINA and REFINB pins default to GPIO on reset. 6.1.1 – Reference Selection Each DAC can be independently enabled with 2.5V internal reference or external reference. Each DAC has two bits in the DAC configuration register (DACCFG) that are used to enable or disable the DAC with either an internal or an external reference.
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DS4830A User’s Guide 6.2.2 – DAC Data Registers (DACD0-DACD7) Bit Name Reset Access 15 0 r BIT 15:12 11:0 * 14 0 r 13 0 r 12 0 r NAME DACDx*[11:0] 11 10 9 8 7 0 rw 0 rw 0 rw 0 rw 0 rw 6 5 DACDx[11:0] 0 0 rw rw 4 3 2 1 0 0 rw 0 rw 0 rw 0 rw 0 rw DESCRIPTION Reserved. The user should write zero to these bits. DACDx: These bits set the DACx output voltage according to reference selection and reference value.
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DS4830A User’s Guide SECTION 7 – ANALOG-TO-DIGITAL CONVERTER (ADC) M U X INTERNAL DIE TEMP SH0 SH1 Internal Offset ADCG2 ADCG3 ADCG4 CONFIGURATION[19] CONFIGURATION[23] WRITE TO ADDATA NUM_SMP ADCONT ADCONV ADEND ADCG1 Current Source For Temperature Measurement ADC SEQ ADCFG=1 ADIDX[4:0] ADC AVG ADCAVG=1 ADIDX[4:0] ADGAIN DATA BUFFER[0] DATA BUFFER[1] ADCFG=0 ADIDX[4:0] 13-BIT ADC CORE INTERNAL REFERENCE A N A L O G VOLTAGE OFFSET (ADVOFF) REFINA REFINB VDD DAC INT REF Reserved Reserved
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DS4830A User’s Guide Table 7-1: ADC Configuration and Data Buffers DATA BUFFER CONFIGURATION/DATA BUFFER SELECTION 0-15 External Channels (0-15 in single-ended or 0-7 in differential) 16 REFINA 17 REFINB 18 VDD (Supply Voltage) 19 DAC Internal Reference 20-21 Reserved, can be used with Location Override 22 Internal Die Temperature 23 Sample and Hold 0 24 Sample and Hold 1 0-24 (Any) ADC Internal Offset (with Location Override) By default, the external channels GP0-15 are general-purpose inputs.
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DS4830A User’s Guide is stopped. Writing a ‘0’ to the ADCONV bit stops the ADC operation at the completion of the current ADC conversion. Writing a ‘1’ to the ADCONV bit when ADCONV bit is already set to ‘1’ is ignored by the ADC controller.
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DS4830A User’s Guide 7.1.4 – Sample and Hold Conversion The DS4830A has two Sample and Hold (S/H) inputs at pins GP2-GP3 and GP12-GP13. These can be independently enabled or disabled by writing to their corresponding bit locations in the Sample and Hold Control register (SHCN). See the Sample and Hold description in Section 8. The Sample and Hold uses data buffer 23 and 24 for S/H0 and S/H1 respectively. The Sample and Hold conversion complete flags are located in the ADST register.
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DS4830A User’s Guide 7.1.7 – ADC Conversion Time The ADC clock is derived from the system clock with a divide ratio defined by the ADC Clock Divider Bits ADCCLK [2:0] in the ADC Control register (ADCN). Each sample takes 15 ADC clock cycles to complete. Two of the 15 ADC clock cycles are used for sample acquisition, and the remaining 13 clocks are used for data conversion. The ADC automatically reads each measurement twice and outputs the average of the two readings.
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DS4830A User’s Guide ADC STARTUP HOLD AND CONVERT SAMPLE 1 SAMPLE 2 SAMPLE 1 HOLD AND CONVERT SAMPLE 2 ADACQ 1 ADCCLK 19 20 ... 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Core Clock delays (ADACQ[3:0]) ADCONV ADDATA ADC DATA VALID Figure 7-4: Extended Acquisition Time 7.1.8 – Location Override By default, the ADC controller stores ADC conversion results in the ADC buffer location corresponding to the channel number (as defined in Table 7.1).
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DS4830A User’s Guide Figure 7-5 shows the ADC frame sequence for the following programmed sequence of ADC channels. 1. CH0: Average of 4 Samples 2. CH4: Average of 8 Samples 3. CH5: Average of 16 Samples 4. CH6: Average of 1 Sample 5. S/H0: Average of 2 Samples 6. S/H1: Average of 4 Samples 7. Internal Temperaute: Average of 16 Samples S/H1 samples will get converted by ADC. End of Sequence. One Sample of Internal Temperature gets chance here. Both S/H0 & S/H1 are ready.
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DS4830A User’s Guide For example, if ADSTART = 0, ADEND = 6 and NUM_SMP = 3 with ADDAINV = 1, then ADDAI is set to ‘1’ after every (NUM_SMP + 1) ADC conversions and every End of Sequence. In the given example, ADDAI is set after 4,7,8,12,14… ADC Samples. Interrupts after 4, 8 and 12 ADC Samples are because of (NUM_SMP+1) configurations and interrupts after 7 and 14 are because of “End of Sequence”. Figure 7-6 demonstrates above ADC example sequence.
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DS4830A User’s Guide 7.2 – ADC Register Descriptions The ADC is controlled by the ADC SFR registers. The PINSEL register is used to configure pins as analog pins for ADC use. Six of the registers, ADST, ADST1, ADADDR, ADCN, RPCFG, REFAVG and ADDATA are used for setup, control, and reading from the ADC. Registers ADCG1-4 and ADVOFF which are used to adjust the gains and offsets applied to ADC results. To avoid undesired operations, the user should not write to bits labeled as “Reserved”. 7.2.
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DS4830A User’s Guide 7.2.2 – ADC Status Register (ADST) Bit Name Reset Access 15 0 r 14 0 r 13 0 r BIT 15:12 11 NAME ENABLE_2X 7 ADCAVG 6 ADCONV 5 ADCFG 4:0 ADIDX[4:0] 12 0 r 11 ENALE_2X 0 rw 10 0 r 9 0 r 8 0 r 7 6 5 4 ADCAVG ADCONV ADCFG 0 0 0 0 rw rw rw rw 3 0 rw 2 1 ADIDX[4:0] 0 0 rw rw 0 0 rw DESCRIPTION Reserved. The user should not write to these bits. ADC Fast Conversion Mode. When ADST.ENABLE_2X = 1, the ADC operates in the fast mode.
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DS4830A User’s Guide 7.2.4 – ADC Status Register (ADST1) Bit Name Reset Access 15 0 r 14 0 r BIT 15:6 5 NAME SH1DAI 4 SH0DAI 3:2 1 INTDAI 0 ADDAI 13 0 r 12 0 r 11 0 r 10 0 r 9 0 r 8 0 r 7 0 r 6 0 r 5 4 SH1DAI SH0DAI 0 0 rw rw 3 0 r 2 0 r 1 0 INTDAI ADDAI 0 0 rw rw DESCRIPTION Reserved. The user should not write to these bits. Sample and Hold 1 Data Available Interrupt Flag.
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DS4830A User’s Guide 7.2.6.1 – ADC Configuration Register (ADDATA when ADCFG = 1 and ADCAVG = 0) When ADCFG = 1 and ADCAVG = 0, writing to the ADDATA register writes to one of the configuration registers. The configuration register written to is selected by the ADIDX[4:0] bits. The ADIDX[4:0] bits are automatically incremented after a write to ADDATA. This allows consecutive writes of ADDATA to setup consecutive configuration registers. The configuration registers are reset to ‘0’ on all forms of reset.
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DS4830A User’s Guide 7.2.6.2 – ADC Average Register (ADDATA when ADCAVG = 1 and ADCFG = 0) When ADCAVG = 1 and ADCFG = 0, writing to the ADDATA register writes to one of the averaging configuration registers. The averaging configuration register written to is selected by the ADIDX[1:0] bits. The ADIDX[1:0] bits are automatically incremented after a write to ADDATA. This allows consecutive writes of ADDATA to setup consecutive average registers. The average registers are reset to ‘0’ on all forms of reset.
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DS4830A User’s Guide 7.2.8 – Temperature Control Register (TEMPCN) The Temperature Control register TEMPCN configures and enables internal die temperature. The Internal Temperature has a dedicated data buffer at address 22. The DS4830A ADC controller forces current into the internal diode and integrates voltage across diode. After integration the voltage is measured at ADC and the voltage is converted into temperature.
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DS4830A User’s Guide 7.2.10 – ADC Voltage Offset Register (ADVOFF) Bit 15 14 13 12 11 12 11 Name S S S 2 2 Reset s s s s s Access rw rw rw rw rw s = special, initial value is dependent on trim settings 10 10 2 s rw 9 9 2 s rw 8 8 2 s rw 7 7 2 s rw 6 6 2 s rw 5 5 2 s rw 4 4 2 s rw 3 3 2 s rw 2 2 2 s rw 1 1 2 s rw 0 0 2 s rw This register contains the ADC voltage offset for the voltage mode. This is calibrated for ADCG1 at the factory to cancel out any offset that may be present in the ADC.
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DS4830A User’s Guide 7.3 – ADC Code Examples 7.3.1 – One Sequence of 4 Voltage Conversions for Ch0 (Diff), Ch1 (Diff), Ch14 (Single), and Ch15 (Single) PINSEL = 0xC00F; //Configure Pin as ADC Ch0 (Diff), Ch1 (Diff), Ch14 (Single) and Ch15(Single) REFAVG_bit.INTREF = 1; //Enable ADC internal reference for(iCounter = 0; iCounter < 1000; iCounter++); //Wait ~1ms to settle ADC internal reference ADCN_bit.ADCONT = 0; //run a single conversion sequence ADST_bit.ADCFG = 1; ADST_bit.
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DS4830A User’s Guide ADST_bit.ADCFG = 0; //set ADDATA to data buffer ADADDR_bit.ADSTART = 0; //start sequence with ADCFG [0] ADADDR_bit.ADEND = 15; //end sequence with ADCFG [15] ADST_bit.ADCONV = 1; //start the conversions while (1) { while (!ADST_bit.ADDAI); //wait for conversions to complete ADST_bit.ADDAI = 0; ADST_bit.ADIDX = 0; //set ADDATA to data buffer [0] for (iCount = 0; iCount < 16; iCount++) ch0 [iCount]= ADDATA; //read and store ch0 voltage to variable } 7.3.
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DS4830A User’s Guide SECTION 8 – SAMPLE AND HOLD Peripheral Clock SHEN* Current Source External Clock The DS4830A has two independent, but identical, Sample and Hold differential channels. Sample and Hold 0 (S/H0) is on GP2-GP3 and Sample and Hold 1 (S/H1) is on GP12-GP13. The sample and hold function can be configured for internal or external triggering. Each sample and hold has a dedicated pin for external trigger.
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DS4830A User’s Guide For proper first sample capturing on power up, the sample and hold should be initialized as explained below. 1. Enable sample and hold for internal sample 2. Apply internal pulse for few µs 3. Wait for conversion to complete, clear the flags and discard the result. 4. Configure S/H according to application requirement without disabling the S/H.
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DS4830A User’s Guide channels and hence their ADC conversion will be delayed. When the FAST_MODE bit is set to ‘0’, the user can issue SHEN pulse every 250µs time interval. Note: When averaging is used for ADC channels or S/H’s, the S/H conversion time slot changes as shown in Figure 7-5 and cannot be guaranteed to get conversion slot in 125µs or 250µs. The S/H conversion time depends upon number of ADC samples to be averaged. 8.1.
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DS4830A User’s Guide Sample Pulse Width with external clock SHEN0/1 or INT_REIG0/1 CLKIN …. …. …. Falling edge (Sample stop) depends upon SSC[3:0] Sample Pulse 300ns min SSC[3:0] = 0 Figure 8-5: Sample Pulse Width with the External Clock As shown in Figure 8-5, the sample pulse width time depends upon the SSC bits value when the external clock is selected (CLK_SEL = 1). 8.1.
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DS4830A User’s Guide 8.1.5 – Sample and Hold Data Reading Each sample and hold has defined data buffer locations where the ADC controller writes sample and hold results after the ADC conversion. The data buffer location 23 and 24 are reserved for Sample and Hold 0 and 1 respectively. The ADC controller uses ADCG1 (1.2V full scale) for ADC conversion of the sampled signal of both sample and holds. 8.1.
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DS4830A User’s Guide 8.2 – Sample and Hold Register Descriptions The sample and hold has two SFRs. These are Sample and Hold Control Register (SHCN) and Sample and Hold Internal Trigger Enable register (SENR). The SHCN register controls both sample and holds. The SENR controls the internal sample pulse for both sample and holds. The sample and hold SFRs are located in module 4. 8.2.
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DS4830A User’s Guide 10 PIN_DIS1 9 PIN_DIS0 8 SH_DUAL 7 6 SH1_ALGN 5 SHDAI1_EN 4 SMP_HLD1 3 CLK_SEL 2 SH0_ALGN 1 SHDAI0_EN 0 SMP_HLD0 this bit is ‘0’, Sample and Hold 0 acts in the normal mode in which Sample and Hold 0 gets a conversion slot in the ADC sequence every 250µs. Pin Discharge Enable 1. Setting this bit to ‘1’ enables the pin discharge function for Sample and Hold 1. The discharge function discharges pin capacitances (GP12-GP13) after the Sample and Hold 1 ADC conversion.
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DS4830A User’s Guide 8.2.2 – Sample and Hold Internal Trigger Enable Register (SENR) Bit Name Reset Access 15 14 13 12 11 10 9 8 7 6 5 4 INT_TRIG_EN1 INT_TRIG1 3 2 - - 1 0 INT_TRIG_EN0 INT_TRIG0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r r r r r r r r r r rw rw r r rw rw BIT 15:6 5 NAME INT_TRIG_EN1 4 INT_TRIG1 3:2 1 INT_TRIG_EN0 0 INT_TRIG0 DESCRIPTION Reserved. The user should write 0 to these bits. Sample and Hold 1 Internal Trigger Enable.
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DS4830A User’s Guide SECTION 9 – QUICK TRIP (FAST COMPARATOR) The DS4830A has 10-bit quick trips with a 16-input analog MUX (Figure 9-1). The MUX selects the quick trip analog input from 16 external channels. The quick trip external channels can be configured to operate as eight fully differential inputs or sixteen single-ended inputs. The quick trip monitors all configured quick trip channels in a round robin sequence.
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DS4830A User’s Guide By default, the external channels GP0-15 are general-purpose input. The DS4830A has the Pin Select Register (PINSEL). The PINSEL register is used to configure the external channels as an analog pin for ADC or/and Quick Trip use. Each bit location in this register corresponds to the ADC/Quick Trip input pin.
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DS4830A User’s Guide times in the QT list). The quick trip list can be filled sequentially with data 05h (channel 5 + single-ended), 06h (channel 6 + single-ended), 17h (channel 7 + differential mode) and 06h (channel 6 + single-ended). See Table 9-2 for the quick trip list configurations. To scan these list registers shown in Table 9-2, the QTSTART bits are set to 0 (0000b) and the QTSTOP bits are set to 3 (0011b). Each channel is compared twice (see Figure 9-2).
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DS4830A User’s Guide Table 9-4: Quick Trip High Threshold Configuration QT LIST NUMBER 0 1 2 3 QTCN = 0x0010; QTDATA = 0x03A3; QTDATA = 0x034E; QTDATA = 0x02FA; QTDATA = 0x02A5; HIGH THRESHOLD VALUE (AS EXAMPLE) 2.2V 2.0V 1.8V 1.6V QTDATA 0x03A3 0x034E 0x02FA 0x02A5 //High Threshold Configuration Register, Index = 0 //2.2V High Threshold Configuration for List0 Configuration //2.0V High Threshold Configuration for List1 Configuration //1.8V High Threshold Configuration for List2 Configuration //1.
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DS4830A User’s Guide 9.2 – Quick Trip Register Descriptions The quick trip has 7 SFRs. These are the Quick Trip Control Register (QTCN), Quick Trip List Register (QTLST), Quick Trip Data Register (QTDATA), Low Trip Interrupt Lower Flag Register (LTIL), High Trip Interrupt Lower Flag Register (HTIL), Low Trip Interrupt High Register (LTIH) and High Trip Interrupt High Register (HTIH). The QTCN register controls the quick trip operation. The QTLIST register defines the list for the quick trip controller.
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DS4830A User’s Guide QTDATA Register map when RW_LST = 0 (in the QTCN Register) Bit Name Reset Access BIT 15:10 9:0 15 14 13 12 11 10 9 8 7 0 r 0 r 0 r 0 rw 0 rw 0 rw 0 r 0 r 0 r NAME QTDATA[9:0] 6 5 4 3 LOW or HIGH THRESHOLD 0 0 0 0 rw rw rw rw 2 1 0 0 rw 0 rw 0 rw DESCRIPTION Reserved. The user should write these bits to ‘0’. a.
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DS4830A User’s Guide 9.2.3 Low Trip Interrupt Lower Register (LTIL) Bit Name Reset Access 15 14 13 12 11 IE[7:0] 10 9 8 7 6 5 4 3 IF[7:0] 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw BIT 15:8 NAME IE[7:0] DESCRIPTION Low Trip Interrupt Enable. This register is used to enable/mask the corresponding LTIL register interrupts.
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DS4830A User’s Guide 9.2.5 Low Trip Interrupt High Register (LTIH) Bit Name Reset Access 15 14 13 12 11 IE[15:8] 10 9 8 7 6 5 4 3 IF[15:8] 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw BIT 15:8 NAME IE[15:8] 7:0 IF[15:8] rw rw DESCRIPTION Low Trip Interrupt Enable. This register is used to enable/mask the corresponding LTIH register interrupts for upper 8 comparisions.
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DS4830A User’s Guide SECTION 10 – I2C-COMPATIBLE MASTER INTERFACE The DS4830A provides an I2C-compatible master controller that allows the DS4830A to communicate with a slave device. The I2C master interface can be setup to provide system interrupts after each I2C event. 10.1 – Detailed Description 10.1.1 – Description of Master I2C Interface The master I2C interface uses the MSDA and MSCL pins. These pins are the master I2C controller’s connection to the SDA and SCL pins of an I2C bus.
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DS4830A User’s Guide Figure 10-1: I2C Clock Generation The master I2C controller’s ability to monitor the state of SCL allows the master to operate with slave devices that stretch the clock. A slave device may clock stretch, or hold SCL low, while it is busy or processing data. The master I2C controller will always release SCL after holding it low for the SCL Low Time duration.
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DS4830A User’s Guide For all of these cases, when the I2C timeout period is reached, the I2CTOI flag will be set. The setting of I2CTOI can generate an interrupt if enabled. If the master I2C controller is in the process of transferring data when the timeout occurs, the controller will abort the current transfer and clear the I2CBUSY flag. The I2CBUS flag will continue to be set until a STOP condition is detected or I2CEN is set to 0. 10.1.
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DS4830A User’s Guide START Generation STOP Generation I2CSTART=1 I2CSTOP=1 I2CBUSY=1 I2CBUSY=1 N Repeated Start ? N I2CBUS = 1 Y Timeout ? N Y Y N Generate STOP Y Transferring Byte? Y Transfering Byte ? N N STOP Detected? Generate START N START Detected? Timeout ? N Y I2CSRI=1 I2CBUS=1 Y N Timeout ? Y I2CSPI=1 I2CBUS=0 Y I2CTOI=1 I2CTOI=1 I2CSTART=0 I2CBUSY=0 I2CSTOP=0 I2CBUSY=0 Figure 10-3: Master I2C-Generated START and STOP 84
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DS4830A User’s Guide 10.1.6 – Generating a STOP To end an I2C transfer, a STOP must be transmitted. A STOP is generated by setting the I2CSTOP bit. The master I2C controller’s flow when attempting to issue a STOP command is shown in Figure 10-3. If the I2CSTOP bit is set when the I2C Controller is in the middle of a byte transfer (after the first bit rising edge), it will wait for the current byte transfer to finish (after the 9 th bit) before generating the STOP condition.
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DS4830A User’s Guide to be set. Once set, writes to I2CBUF_M will be ignored. The first bit of data (most significant bit) will be shifted to SDA when SCL is low. Each of the next seven bits will then be shifted following high to low transitions of SCL. Following the 8th bit of data (least significant bit) being shifted to SDA, the SDA line will be released by the DS4830A master controller. This allows the slave to signal an ACK or NACK during the 9th clock cycle.
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DS4830A User’s Guide 10.1.9 – Receiving Data The DS4830A I2C Master Controller enters data reception mode after transmitting a slave address with the R/W bit (I2CMODE) set to a 1. The steps of data reception are shown in Figure 10-5. After transmitting the slave address, the master controller will switch to receiver mode and automatically begin outputting SCL clock pulses and shifting in data from SDA.
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DS4830A User’s Guide 10.1.10 – I2C Master Clock Stretching The Master I2C Controller is capable of clock stretching at the end of each transfer cycle. Clock stretching is when SCL is held low. If the I2C Clock Stretch Enable bit (I2CSTREN) is set to a 1, the I2C controller will hold SCL low after the clock pulse defined by the I2C Clock Stretch Select bit (I2CSTRS). If I2CSTRS=0, the I2C controller will hold SCL low after the falling edge of the 9th clock pulse.
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DS4830A User’s Guide 10.1.12 – Alternate Location The DS4830A has 3-Wire, SPI and I2C Master on the same pins and some application may need the I2C Master and 3-Wire or SPI interfaces. To support such applications, the DS4830A provides an I2C Master alternate location. When I2CCN_M bit 12 is set to ‘1’, the DACPW4 and DACPW5 pins are used as I2C SDA and I2C SCL pins as I2C Master alternate locations. 10.1.
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DS4830A User’s Guide 10.2 – I2C Master Controller Register Description Following are the registers that are used to control the I2C Master Interface, which is the MSDA and MSCL pins. These registers are used to control the I2C master interface if it is operating as either a master or slave. The bit descriptions below detail how to use these registers when operating in master mode. When operating in slave mode, some of the bits and registers have different functionality.
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DS4830A User’s Guide 10.2.2 – I2C Master Status Register (I2CST_M) Bit Name Reset Access 15 14 I2CBUS I2CBUSY 0 0 r* r* 13 0 r 12 11 10 9 8 7 I2CAMI2 I2CSPI I2CSCL I2CROI I2CGCI I2CNACKI 0 0 0 0 0 0 rw rw r* rw rw rw* 6 0 r 5 4 3 2 I2CAMI I2CTOI I2CSTRI I2CRXI 0 0 0 0 rw rw rw* rw* 1 I2CTXI 0 rw 0 I2CSRI 0 rw * Set by hardware only.
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DS4830A User’s Guide 10.2.3 – I2C Master Interrupt Enable Register (I2CIE_M) Bit Name Reset Access 15 0 r 14 0 r 13 0 r BIT 15:12 11 NAME Reserved I2CSPIE 10 I2CAMI2IE 9 I2CROIE 8 I2CGCIE 7 I2CNACKIE 6 5 Reserved I2CAMIE 4 I2CTOIE 3 I2CSTRIE 2 I2CRXIE 1 I2CTXIE 0 I2CSRIE 12 0 r 11 10 9 8 7 I2CSPIE I2CAMI2IE I2CROIE I2CGCIE I2CNACKIE 0 0 0 0 0 rw rw rw rw rw 6 0 r 5 4 3 2 1 0 I2CAMIE I2CTOIE I2CSTRIE I2CRXIE I2CTXIE I2CSRIE 0 0 0 0 0 0 rw rw rw rw rw rw DESCRIPTION Reserved.
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DS4830A User’s Guide 10.2.5 – I2C Master Clock Control Register (I2CCK_M) Bit Name Reset Access 15 14 13 0 rw 0 rw 0 rw BIT NAME 15:8 I2CCKH[7:0] 7:0 I2CCKL[7:0] 12 11 I2CCKH[7:0] 0 0 rw rw 10 9 8 7 6 5 0 rw 1 rw 0 rw 0 rw 0 rw 0 rw 4 3 I2CCKL[7:0] 0 0 rw rw 2 1 0 1 rw 0 rw 0 rw DESCRIPTION I2C Clock High Period. These bits define the high period of the I2C clock. This period is defined by the number of system clocks.
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DS4830A User’s Guide SECTION 11 – I2C-COMPATIBLE SLAVE INTERFACE The DS4830A provides an I2C-compatible slave controller that allows communication with a host device and supports four user-programmable slave addresses. The DS4830A I2C slave controller can support 400kHz I2C operation with a host without clock stretching. The DS4830A I2C slave interface also has a dedicated 8-byte transmit page for each slave and 8-byte receive FIFO (shared between all four slaves).
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DS4830A User’s Guide 11.1 – Detailed Description The I2C slave controller has two different modes that can be used to transmit and receive data. The first option transmits and received data one byte at a time. An advanced mode uses 8-byte buffers for transmiting and receiving data, which is enabled by setting the TXPG_EN bit in the I2CTXFIE and the FIFO_EN bit in the I2CRXFIE registers. Using this advanced mode of operation, the DS4830A can support 400kHz I2C operation without clock stretching. 11.1.
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DS4830A User’s Guide • Matched Slave Address I2CSLA_S I2CSLA2_S I2CSLA3_S I2CSLA4_S Clears the I2CBUSY flag. CUR_SLA.SLA[3:0] 1 2 4 8 Upon completion of the slave data byte (7 bits of slave address + R/W bit + ACK/NACK), the I2C slave controller enters one of the following three states. • Data Transmit: The slave address matched and the R/W bit is ‘1’. The host is now expecting data from the DS4830A. The I2C slave controller retains control of the SDA line so data can be transmitted to the host.
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DS4830A User’s Guide 11.1.6 – Advanced Mode Operation RX FIFO and TX Pages The DS4830A I2C slave controller has a few features that make 400kHz I2C communication without clock stretching possible.
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DS4830A User’s Guide Receiving Slave Address Transmitting Data Detect I2C Start I2CSRI = 1 I2CBUS = 1 I2CBUSY = 1 Update Transmit Pages at the I2C Start Interrupt Receiving Data Detect 1st SCL Rising Edge I2CBUSY = 1 Receive Addr[6:0] + /R\W No Matched Enabled Slave Addresses Yes Transmit I2CACK Set I2CMODE bit according to /R\W Is Active Transmit Page Generated Threshold Interrupt No Transmit Shift Register Byte, MSB First I2CBUSY = 0 No 8 Bits Received ? Yes 8 Bits Transmit ? Yes RX FIF
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DS4830A User’s Guide • • • Sets the I2CST_S.I2CTXI flag to indicate that the I2C slave controller has transmitted a byte. This can generate an interrupt if enabled. Sets or clears the I2CST_S.I2CNACKI flag to reflect the received acknowledge bit. The setting of I2CNACKI can generate an interrupt if enabled. Clears the I2CST_S.I2CBUSY flag to indicate that the I2C slave controller is not actively participating in the transfer of data.
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DS4830A User’s Guide 11.1.8 – Receiving Data The I2C Slave Controller enters data reception mode after receiving a matching slave address with the R/W bit set to 0. The steps of data reception are shown in Figure 11-2 and Figure 11-4. The reception process begins when the I2C slave controller detects the first rising edge of SCL. This rising edge sets I2CBUSY bit to ‘1’ and clocks the first bit (MSB) of data from SDA into the data shift register. 11.1.8.
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DS4830A User’s Guide Figure 11-5: Slave I2C Clock Stretching Normally when the I2C slave controller is receiving data, the value of I2CACK is sent after the falling edge of the 8th clock. However, if clock stretching is enabled after the 8th clock, the I2C slave controller continues to output the I2CACK bit until clock stretching is released by software. This allows software time to inspect data that is received before responding with an appropriate acknowledge bit.
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DS4830A User’s Guide 11.1.10 – SMBus Timeout The I2C slave controller can also be used for SMBus or PMBus™ communication. To maintain SMBus compatibility, a 30ms timer is implemented by the I2C slave controller. The purpose of this timer is to issue a timeout interrupt when SCL is low for greater than 30ms. The timer only starts when none of the following conditions are true: 1. The I2C slave controller is in the idle state and there are no communications on the I2C bus.
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DS4830A User’s Guide 11.2 – I2C Slave Controller Register Description Following are the registers that are used to control the I2C Slave Interface. 11.2.1 – I2C Slave Control Register (I2CCN_S) Bit 15 14 13 12 11 10 9 8 7 6 5 4 ADDR4EN ADDR3EN ADDR2EN SMB_MOD I2CSTREN I2CGCEN I2CACK I2CSTRS Name 0 0 0 0 0 0 0 0 0 0 0 0 Reset r r rw rw rw rw rw* rw* r r rw* rw* Access * Unrestricted Read. Unrestricted write access when I2CBUSY=0. Writes to I2CEN are disabled when I2CBUSY=1.
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DS4830A User’s Guide 11.2.2 – I2C Slave Status Register (I2CST_S) Bit 15 14 Name I2CBUS I2CBUSY Reset 0 0 Access r* r* * Set by hardware only.
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DS4830A User’s Guide 11.2.3 – I2C Slave Interrupt Enable Register (I2CIE_S) Bit Name Reset Access 15 0 r 14 0 r 13 0 r 12 0 r 11 0 r 10 9 8 7 - I2CROIE I2CGCIE I2CNACKIE 0 0 0 0 r rw rw rw 6 5 4 3 2 1 0 - I2CAMIE I2CTOIE I2CSTRIE I2CRXIE I2CTXIE I2CSRIE 0 0 0 0 0 0 0 r rw rw rw rw rw rw BIT NAME DESCRIPTION 15:10 9 Reserved I2CROIE 8 I2CGCIE 7 I2CNACKIE 6 5 Reserved I2CAMIE 4 I2CTOIE 3 I2CSTRIE 2 I2CRXIE 1 I2CTXIE 0 I2CSRIE Reserved. The user should not write to these bits.
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DS4830A User’s Guide 11.2.4 – I2C Slave Status2 Register (I2CST2_S) Bit Name Reset Access 15 0 r 14 0 r 13 0 r 12 0 r 11 0 r 10 0 r 9 0 r 8 0 r 7 0 r 6 0 r 5 4 3 I2CSPI SADI MADI 0 0 0 rw rw rw 2 0 r 1 I2CXFRON 0 rw 0 0 r BIT NAME DESCRIPTION 15:6 5 Reserved I2CSPI 4 SADI 3 MADI 2 1 Reserved I2CXFRON 0 Reserved Reserved. The user should not write to these bits. I2C Slave STOP Interrupt Flag. This bit is set to '1' when a STOP condition is detected.
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DS4830A User’s Guide 11.2.6 – I2C Slave Address Registers (I2CSLA_S, I2CSLA2_S, I2CSLA3_S and I2CSLA4_S) I2CSLA_S Bit Name Reset* Access 15 0 r 14 0 r 13 0 r 12 0 r 11 0 r 10 0 r 9 0 r 8 0 r 7 A6 0 rw 6 A5 0 rw 5 A4 1 rw 4 A3 1 rw 3 A2 0 rw 2 A1 1 rw 1 A0 1 rw 0 I2CMode 0 rw 10 0 r 9 0 r 8 0 r 7 A6 0 rw 6 A5 0 rw 5 A4 0 rw 4 A3 0 rw 3 A2 0 rw 2 A1 0 rw 1 A0 0 rw 0 I2CMode 0 rw * Default value of I2CSLA_S is 36h.
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DS4830A User’s Guide 11.2.8 – Memory Map Address Register (MADDR) Bit Name Reset Access 15 0 r 14 0 r 13 0 r 12 ROLLOVR 0 rw 11 0 r 10 9 8 PAGE[2:0] 0 0 0 rw rw rw 7 6 0 rw 0 rw 5 4 3 2 MEM_ADDR[7:0] 0 0 0 0 rw rw rw rw 1 0 0 rw 0 rw BIT NAME DESCRIPTION 15:13 12 Reserved ROLLOVR 11 10:8 7:0 Reserved PAGE MEM_ADDR Reserved. The user should not write to these bits.
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DS4830A User’s Guide 11.2.12 – Current Slave Address Register (CUR_SLA) Bit Name Reset Access 7 MADDR_EN14 0 rw 6 MADDR_EN3 0 rw 5 MADDR_EN2 0 rw 4 MADDR_EN1 0 rw 3 2 1 0 0 rw 0 rw SLA[3:0] 0 rw 0 rw BIT NAME DESCRIPTION 15:8 7 Reserved MADDR_EN4 6 MADDR_EN3 5 MADDR_EN2 4 MADDR_EN1 3:0 SLA[3:0] Reserved. The user should not write to these bits. Memory Address Detection Enable 4: Setting this bit to ‘1’, enables the memory address detection as described in section 11.1.6.
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DS4830A User’s Guide 11.2.15 – I2C TX Page Interrupt Enable Register (I2CTXFIE) Bit Name Reset Access 7 TXPG_EN 0 rw 6 0 r 5 0 r 4 0 r 3 0 r 2 0 r 1 THSH 0 rw 0 0 r BIT NAME DESCRIPTION 7 6:2 1 0 TXPG_EN Reserved THSH Reserved TX PAGE ENABLE: Setting this bit to ‘1’, enables the TX PAGE for all enabled slave addresses. Reserved. The user should not write to these bits. TX Page Threshold Reach Enable: Setting this bit to ‘1’, enables TX page threshold reach interrupt. Reserved.
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DS4830A User’s Guide SECTION 12 – SERIAL PERIPHERAL INTERFACE (SPI) The DS4830A provides two independent Serial Peripheral Interfaces (SPI) – one defined as SPI Master and SPI Slave. Each SPI module of the DS4830A microcontroller provides an independent serial communication channel to communicate synchronously with peripheral devices in a multiple master or multiple slave system.
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DS4830A User’s Guide controls whether the active or inactive clock edge is used to latch the data. When CKPHA is set to 1, data is sampled on the inactive clock edge (clock returning to the idle state). When CKPHA is set to 0, data is sampled on the active clock edge (clock transition to the active state). Together, the CKPOL and CKPHA bits allow four possible SPI data transfer formats illustrated in Figure 12-2 and Figure 12-3. The Slave Select signal can remain asserted between successive transfers.
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DS4830A User’s Guide 12.1.2 – SPI Character Lengths To flexibly accommodate different SPI transfer data lengths, the character length for any transfer is user configurable via the Character Length Bit (CHR) in the SPI Configuration Register. These are independently configurable for the master and slave SPI. The CHR bit allows selection of either 8-bit or 16-bit transfers. When CHR is 0, the character length is 8-bits; when CHR is set to 1, the character length is 16 bits.
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DS4830A User’s Guide 12.2.3 – Write Collision While Busy A write collision occurs if an attempt to write the SPIB data buffer is made during a transfer cycle (STBY=1). Since the shift register is single buffered in the transmit direction, writes to SPIB are made directly into the shift register. Allowing the write to SPIB while another transfer is in progress could easily corrupt the transmit/receive data.
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DS4830A User’s Guide master’s SPI Clock SFR. The SPI transfer format is selected by the master device using two bits SPI Clock Polarity (CKPOL) and Clock Phase in the SPI Configuration Register.
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DS4830A User’s Guide 12.4.3 – SPI Master Register Descriptions SPI Master Module has four SFR registers. These are SPICN_M, SPICF_M, SPICK_M and SPIB_M. The SPI control register SPICN_M and SPI configuration register SPICF_M controls and configures the Serial Peripheral Interface, respectively. The SPI Clock Register SPICK_M configures SPI Baud rate in Master mode. The SPI Buffer SPIB_M is used in SPI data transfer. SPI Master SFRs are located in Module 5. 12.4.3.
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DS4830A User’s Guide 12.4.3.2 – SPI Configuration Register (SPICF_M) Bit Name Reset Access 7 ESPII 0 rw 6 SAS 0 rw 5 0 r 4 0 r 3 0 r 2 CHR 0 rw 1 CKPHA 0 rw 0 CKPOL 0 rw BIT 7 NAME ESPII DESCRIPTION SPI Interrupt Enable. Setting this bit to ‘1’ enables the SPI interrupt when MODF, WCOL, ROVR or SPIC flags are set. Clearing this bit to ‘0’ disables the SPI interrupt. 6 SAS 5:3 2 Reserved CHR 1 CKPHA 0 CKPOL Slave Active Select. In Master mode, this is used only when mode fault is enabled.
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DS4830A User’s Guide 12.5 – SPI Slave The DS4830A has the following SPI interface signals. FUNCTIONAL NAME EXTERNAL PIN NAME SSPIDO: Output from serial shift register (MISO) GP6 SSPIDI: Input to serial shift register (MOSI) SDA SSPICK: Serial shift clock from SPI master (SPICK) SCL SSPICS: Slave select input (CS) GP7 12.5.
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DS4830A User’s Guide 12.5.4 – SPI Slave Register Descriptions SPI Slave Module has four SFR registers. These are SPICN_S, SPICF_S, SPICK_S, and SPIB_S. The SPI control register SPICN_S and SPI configuration register SPICF_S controls and configures the Serial Peripheral Interface respectively. The SPI Clock Register SPICK_S is not used in SPI Slave mode as SPI clock is driven by SPI Master. The SPI Buffer SPIB_S is used in SPI data transfer. SPI Slave SFRs are located in Module 1. 12.5.4.
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DS4830A User’s Guide 12.5.4.2 – SPI Configuration Register (SPICF_S) Bit Name Reset Access 7 ESPII 0 rw 6 SAS 0 rw 5 0 r 4 0 r 3 0 r 2 CHR 0 rw 1 CKPHA 0 rw 0 CKPOL 0 rw BIT 7 NAME ESPII DESCRIPTION SPI Interrupt Enable. Setting this bit to ‘1’ enables the SPI interrupt when MODF, WCOL, ROVR or SPIC flags are set. Clearing this bit to ‘0’ disables the SPI interrupt. 6 SAS 5:3 2 Reserved CHR 1 CKPHA 0 CKPOL Slave Active Select.
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DS4830A User’s Guide SECTION 13 – 3-WIRE The DS4830A has proprietary 3-Wire master interface for communication with MAXIM 3-wire laser drivers (which supports MSB first 3-wire protocol). The 3-wire communication mode operates similar to SPI mode. However, in the 3-wire mode, there is one bi-directional I/O instead of separate data in and data out signals. The 3-wire interface consists of the MCS, MDIO and MCL. The 3-Wire Master interface reads data on the falling edge of MCL.
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DS4830A User’s Guide 13.1.1.1 – Write Mode (RWN=0) The 3-Wire master generates 16 clock cycles on MCL pin. It outputs 16-bits (MSB first DADDR data) to the MDIO line at the falling edge of the MCL. After completion of 16 clocks, the 3-Wire BUSY flag is cleared and the data transfer complete flag TWI is set to ‘1’ which generates interrupt if enabled. The master closes the transmission by setting the MCS to ‘0’. 13.1.1.2 – Read Mode (RWN=1) The 3-Wire master generates 16 clock cycles at MCL.
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DS4830A User’s Guide 13.2 – 3-Wire Register Descriptions The 3-Wire interface is controlled by two SFR registers. These are the 3-Wire Control Register TWR and Data and Address Register DADDR. The TWR register configures and controls 3-Wire interface. The DADDR is used in 3-Wire read and write operation. These registers are located at Module 2. 13.2.
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DS4830A User’s Guide SECTION 14 – PWM The DS4830A provides 10 independent PWM output pins that can be used to create DC-DC power supply controllers or a Thermoelectric Cooler Controller (TECC) Refer to Application Note 5424: Thermoelectric Cooler Control Using the DS4830 Optical Microcontroller. 14.1 – Detailed Description The DS4830A provides 10 independently configurable PWM outputs. The DS4830A PWM controller has 3 SFRs PWMCN, PWMDATA and PWMSYNC for configuration and control of the 10 PWM outputs.
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DS4830A User’s Guide READ OR WRITE TO PWMDATA DCYC0 (Ch0) PWMCN.REG_SEL = 00b DUTY CYCLE REGISTER PWMCN.PWM_SEL =n DCYC9 (Ch9) PWMCFG0 (Ch0) PWMCN.REG_SEL = 01b PWM CONFIGURATION PWMCN.PWM_SEL =n PWMCFG9 (Ch9) PWMDLY0 (Ch0) PWMCN.REG_SEL = 1xb DELAY REGISTER PWMCN.PWM_SEL =n PWMDLY9 (Ch9) PWMDATA REGISTER Note: n = 0 to 9 Figure 14-1: Illustration of PWMDATA and PWMCFG SFRs 14.1.2 – PWMSYNC SFR Different channels can be synchronized using the PWMSYNC register.
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DS4830A User’s Guide 14.
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DS4830A User’s Guide PWM Output High Time DCYCn = 128 PWM Output Low Time 128 Cycles 384 Cycles PWM Frame = 512 Cycles 9-bit PWM Operation in Normal Mode Figure 14-4: PWM Duty Cycle Set to 128 with 9-Bit Resolution 14.2.2 – PWM Configuration Register (PWMCFGn) This register allows independent configuration of a PWM Channel. Each PWM Channel can be independently disabled or enabled. Each output can have from 7 to 16 bits of resolution and can be inverted.
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DS4830A User’s Guide Table 14-2: Number of Slots for Each Resolution PS[1:0]= 00 RES_SEL[3:0] Resolution 7 8 9 10 11 12 13 14 15 16 16 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b >1001b PS[1:0]= 01 PS[1:0]= 10 Number of Slots 1 1 1 1 1 2 2 4 4 8 8 16 16 32 32 64 64 128 128 256 128 256 1 1 1 1 2 4 8 16 32 64 64 PS[1:0]= 11 1 2 4 8 16 32 64 128 256 512 512 Pulse Spreading Method The DS4830A PWM controller uses a delta sigma algorithm to distribute the duty cycle uniformly among the slots.
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DS4830A User’s Guide 10-bit resolution PWM Operation with 8-Slot pulse spreading mode PWM Frame = 1024 Cycles 1-Slot = 128 Cycles Slot 1 Slot 2 PWM Output Low Time PWM Output High Time Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Slot 8 Next Cycle Slot 1 DCYCn = 128 16 Cycles 112 Cycles DCYCn = 129 17 Cycles 111 Cycles DCYCn = 130 DCYCn = 131 DCYCn = 132 DCYCn = 133 DCYCn = 134 DCYCn = 135 DCYCn = 136 17 Cycles 111 Cycles Figure 14-5: Duty Cycle Distribution with 8-Slot Pulse Spreading (PS[1:0] =
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DS4830A User’s Guide See Tables 14-4a, 14-4b, and 14-4c for slot frequencies at various resolutions and pulse-spreading options with the different PWM source clock frequencies. Table 14-4a: Slot Frequencies for Various Resolution and Pulse Spreading with Core Clock = 10MHz Source = Core Clock (10MHz) Pulse Spreading (PS[1:0]) Resolution Frame Frequency (Hz) 00 01 10 11 Slot Frequency (Hz) 7 78125 78125 78125 78125 78125 8 39062.5 39062.5 39062.5 39062.5 78125 9 19531.25 19531.25 19531.
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DS4830A User’s Guide Table 14-4c: Slot Frequencies for Various Resolution and Pulse Spreading with External Clock = 128MHz Source = External Clock (128MHz) Pulse Spreading (PS[1:0]) Resolution Frame Frequency (Hz) 00 01 10 11 Slot Frequency (Hz) 7 1000000 1000000 1000000 1000000 1000000 8 500000 500000 500000 500000 1000000 9 250000 250000 250000 500000 1000000 10 125000 125000 250000 500000 1000000 11 62500 125000 250000 500000 1000000 12 31250 125000 250000 500000
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DS4830A User’s Guide Programmed Delay. Max 8 Bits (256 clock cycles), for 10 bits of Resolution & 4-slot pulse spreading Source Clock Figure 14-6: PWM Delay Operation without Pulse Spreading 14.2.3.1 – PWM DELAY with PWMSYNC SFR The PWM channels to be synchronized must have the same configurations (Resolution, Pulse Spreading option, Clock source etc.). The delays on the two channels can be different. After the synchronization, the programmed delay is maintained as shown in Figure 14-7.
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DS4830A User’s Guide 14.3.1 – PWM Control Register (PWMCN) The PWMCN register is used to setup and start the PWM Output. To avoid undesired operation, the user should not modify the “Reserved” bits in the PWMCN registers. Bit Name Reset Access 15 0 r 14 0 r 13 0 r BIT 15:13 12 NAME M_EN 11:9 8 UPDATE 7:4 PWM_SEL[3:0] 12 M_EN 0 rw 11 0 r 10 0 r 9 0 r 8 UPDATE 0 rw 7 0 rw 6 5 PWM_SEL[3:0] 0 0 rw rw 4 0 rw 3 0 r 2 0 r 1 0 REG_SEL[1:0] 0 0 rw rw DESCRIPTION Reserved.
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DS4830A User’s Guide 14.3.2 – PWM Data Register (PWMDATA) Bit Name Reset Access BIT 15:0 15 14 13 12 11 10 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw NAME PWMDATA[15:0] 9 8 7 6 PWMDATA[15:0] 0 0 0 0 rw rw rw rw 5 4 3 2 1 0 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw DESCRIPTION PWM Data. The PWM Data Register is used for configurations for various PWM channels.
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DS4830A User’s Guide 14.3.2.2 – Local Register PWMCFGn (through PWMDATA [15:0] Bit Name Reset Access 15 INV 14 - 13 12 ALT_ PWMEN LOC 9 8 CLK_SEL 7 6 - 5 PS1 4 PS0 3 2 1 RES[3:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw NAME INV 14 13 ALT_LOC 12 PWMEN 11:10 9:8 CLK_SEL[1:0] 3:0 10 - rw BIT 15 7:6 5:4 11 PS[1:0] RES[3:0] PWMCN REG_SEL = 01b PWMDATA[15:0]  PWMCFGn[15:0] DESCRIPTION Invert PWM Output.
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DS4830A User’s Guide 14.3.2.3 – Local Register PWMDLYn BIT 15:0 NAME PWMDLYn[15:0] PWMCN REG_SEL = 1xb PWMDATA[15:0]  PWMDLY[15:0] DESCRIPTION Delay Setting Register. When REG_SEL[1:0] is set to 1xb, the PWMDATA register points to the Delay Setting Register of PWM channel selected by PWM_SEL[3:0] bits in the PWMCN register. The Delay Setting Register is a 16-bit register, which is used for providing starting delay. Using this Delay Setting Register multiphase operation can be configured.
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DS4830A User’s Guide 14.4 – PWM Output Code Examples 14.4.
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DS4830A User’s Guide SECTION 15 – GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PINS 15.1 – Overview The DS4830A provides general-purpose input/output (GPIO) functionality on 31 pins. In addition to the GPIO functionality, each of these pins is multiplexed with at least one other function, which is classified as “Special Function.” Special functions override the GPIO register settings of the port pin when they are enabled.
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DS4830A User’s Guide Table 15-1: GPIO Pins and Multiplexed Functions Port Pin Name Index Pin No. Default Special Function Function-1 P0.0 GP12 19 GPIO ADC-S12 P0.1 GP13 20 GPIO ADC-S13 P0.2 GP14 21 GPIO ADC-S14 P0.3 GP15 22 GPIO ADC-S15 P0.4 DACPW0 32 GPIO DAC0 P0.5 DACPW1 33 GPIO DAC1 P0.6 PW8 30 GPIO PW8 P0.7 PW9 29 GPIO PW9 Special function-1 enable PINSEL.12 = 1 & ADDATA.DIFF = 0 PINSEL.13 = 1 & ADDATA.DIFF = 0 PINSEL.14 = 1 & ADDATA.DIFF = 0 PINSEL.
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DS4830A User’s Guide programming flexibility for any application. The associated registers and their module addresses are listed in Table 15-2. The user should not write to any reserved bits as this may cause undesired behavior.
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DS4830A User’s Guide 15.2 – GPIO Port Register Descriptions The DS4830A has 4 ports P0, P1, P2 and P6. Each port has 8 pins (exception is P6 which has 7 pin only). The GPIO operation is to control/monitor through PDp, POp and PIp (p = 0, 1, 2 and 6). These ports are multiplexed with various functions like ADC, DAC, Sample and Hold, PWM, I2C, 3-Wire, SPI etc. Additionally, these ports also provide GPIO interrupts on all of the pins.
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DS4830A User’s Guide 15.2.5 – GPIO Port External Interrupt Flag Register (EIF0, EIF1, EIF2, and EIF6) Bit # 7 6 5 4 3 2 Name IFPp_7 IFPp_6 IFPp_5 IFPp_4 IFPp_3 IFPp_2 Reset 0 0 0 0 0 0 Access rw rw rw rw rw rw 1 IFPp_1 0 rw 0 IFPp_0 0 rw These bits are set when a negative edge (IESPp.n = 1) or a positive edge (IESPp.n = 0) is detected on the Pp.n pin. Setting any of the bits to 1 will generate an interrupt to the CPU if the corresponding interrupt is enabled.
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DS4830A User’s Guide SECTION 16 – GENERAL-PURPOSE TIMERS The DS4830A has two identical 16-bit general-purpose timers. Each timer has the following, • • • • Two modes - Free synchronous and Compare Three Clock source selection options - Core clock, Peripheral clock and External clock 6 prescalers Interrupt feature in both modes.
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DS4830A User’s Guide interrupt if enabled. When the match occurs, the timer reloads the GTV register with 0x0000 at the next timer clock. In compare mode, the GTC register should be written first before setting the GTR bit. 16.1.2 – Clock Selection There are three timer clock sources available in each timer module, core clock, peripheral clock and external clock. The peripheral clock is twice the core clock. The external clock can be between 20MHz to 133MHz.
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DS4830A User’s Guide 16.2 – Timer Register Descriptions Each General Timer module has three independent SFR registers. These are GTCN, GTV and GTC. The General Timer Control Register GTCN controls the timer operation. The General Timer Value Register GTV is the Timer Value register and is incremented every timer clock when enabled. The General Timer Compare Register GTCx is used in the timer compare mode only. Timer 1 and 2 SFRs are located in module 0 and 3 respectively. 16.2.
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DS4830A User’s Guide 16.2.2 – General Timer Value Register (GTV1 and GTV2) Bit Name Reset Access 15 14 13 12 11 10 9 0 r 0 r 0 r 0 r 0 r 0 r 0 r 8 7 GTV(1,2) 0 0 r r 6 5 4 3 2 1 0 0 r 0 r 0 r 0 r 0 r 0 r 0 r 6 5 4 3 2 1 0 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 16.2.
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DS4830A User’s Guide SECTION 17 – SUPPLY VOLTAGE MONITOR (SVM) The DS4830A provides feature to allow monitoring its power supply. The Supply Voltage Monitor (SVM) monitors the VDD power supply and can alert the processor through an interrupt if VDD falls below a programmable threshold. The DS4830A provides the following power monitoring features: • SVM compares VDD against a programmable threshold from approximately 2.3V to 3.5V.
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DS4830A User’s Guide SECTION 18 – HARDWARE MULTIPLIER MODULE The hardware multiplier module can be used by the DS4830A to support high-speed multiplications. The hardware multiplier module is equipped with two 16-bit operand registers, a 32-bit read-only result register, and an accumulator of 48-bit width. The multiplier can complete a 16-bit x 16-bit multiply-and-accumulate/subtract operation in a single cycle.
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DS4830A User’s Guide via the MCNT register bits, loading the prescribed number of operands triggers the respective multiply, multiplyaccumulate/subtract or multiply-negate operation. 18.3 – Register Output Selection The Hardware Multiplier implements the MC Register Write Select (MCW) control bit so that writing of the result to the MC2:MC0 registers can be blocked to preserve the MC registers (accumulator).
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DS4830A User’s Guide The specified hardware multiplier operation begins when the final operand(s) is loaded and will complete in a single cycle. The read-only MC1R, MC0R result registers can be accessed in the very next cycle unless accumulation/subtraction with MC2:0 is requested (MCW = 0 and MMAC = 1), in which case, one cycle is required so that stable data can be read. When MCW = 0, the MC2:0 registers always require one wait cycle before the operation result is accessible.
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DS4830A User’s Guide 18.5 – Hardware Multiplier Peripheral Registers The hardware multiplier registers are detailed below. Addresses of registers are given as “Mx[yy]” where x is the module number (from 0 to 5 decimal) and yy is the register index (from 00h to 1Fh hexadecimal).
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DS4830A User’s Guide 18.5.1 – Multiplier Control Register (MCNT) Bit Name Reset Access BIT 7 OF 0 r 7 NAME OF 6 MCW 5 CLD 4 SQU 3 OPCS 2 MSUB 1 MMAC 0 SUS 6 MCW 0 rw 5 CLD 0 rw 4 SQU 0 rw 3 OPCS 0 rw 2 MSUB 0 rw 1 MMAC 0 rw 0 SUS 0 rw DESCRIPTION Overflow Flag. This bit is set to logic 1 when an overflow occurred for the last operation. This bit can be set for accumulation/subtraction operations or unsigned multiply-negate attempts.
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DS4830A User’s Guide 18.5.2 – Multiplier Operand A Register (MA) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name MA[15:0] Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Access rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Multiplier Operand A: This operand A register is used by the application code to load 16-bit values for multiplier operations. 18.5.
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DS4830A User’s Guide 18.5.9 – MAC Select Register (MACSEL) Bit Name Reset Access BIT 7:1 0 7 0 r NAME MACRSEL 6 0 r 5 0 r 4 0 r 3 0 r 2 0 r 1 0 r 0 MACRSEL 0 rw DESCRIPTION Reserved MAC Registers Select Register. The device has internally two sets of MAC registers. Using this bit one of two MAC registers is selected which allows uninterruptible MAC operation. 18.5.
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DS4830A User’s Guide 18.6 – Hardware Multiplier Examples The following are code examples of multiplier operations.
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DS4830A User’s Guide SECTION 19 – WATCHDOG TIMER 19.1 - Overview The Watchdog Timer is a user programmable clock counter that can serve as a time-base generator, an event timer, or a system supervisor. As can be seen in Figure 19-1, the timer is driven by the main system clock and is supplied to a series of dividers. If the watchdog interrupt and the watchdog reset are disabled (WDCN.EWDI = 0 and WDCN.EWT = 0), the watchdog timer and its input clock are disabled.
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DS4830A User’s Guide Table 19-1: Watchdog Operating States EWT EWDI WDIF ACTIONS x X 0 No interrupt has occurred. 0 0 x Watchdog disable, clock is gated off. 0 1 1 Watchdog interrupt has occurred. No interrupt has been generated. Watchdog reset will occur in 512 system 1 0 1 clock cycles if RWT is not set or WDIF not cleared. Watchdog interrupt has occurred. Watchdog reset will occur in 512 system 1 1 1 clock cycles if RWT is not set or WDIF not cleared. 19.2.
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DS4830A User’s Guide Table 19-2: Watchdog Timer Control Register Bits (WDCN) Bit 7 6 5 4 3 2 Name POR EWDI WD1 WD0 WDIF WTRF Reset s* s* 0 0 0 s* Access rw rw rw rw rw rw *Bits 5, 4, 3 and 0 are cleared to 0 on all forms of reset; for others, see individual bit descriptions. BIT 7 NAME POR 6 EWDI 5:4 WD[1:0] WDIF 2 WTRF 1 EWT 0 RWT 0 RWT 0 rw DESCRIPTION Power-On Reset Flag: This bit is set to 1 whenever a power-on/brownout reset occurs. It is unaffected by other forms of reset.
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DS4830A User’s Guide SECTION 20 – TEST ACCESS PORT (TAP) The DS4830A incorporates a Test Access Port (TAP) and TAP controller for communication with a host device across a 4-wire synchronous serial interface. The TAP may be used by the DS4830A to support in-system programming and/or in-circuit debug. The TAP is compatible with the JTAG IEEE standard 1149 and is formed by four interface signals described in Table 20-1. For detailed information on the TAP and TAP controller, refer to IEEE STD 1149.
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DS4830A User’s Guide 20.1 – TAP Controller The TAP controller is a synchronous state machine that responds to changes at the TMS and TCK signals. Based on its state transition, the controller provides the clock and control sequence for TAP operation. The performance of the TAP is dependent on the TCK clock frequency. The maximum TCK clock frequency should be limited to 1/8 the system clock frequency. This section provides a brief description of the state machine and its state transitions.
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DS4830A User’s Guide 20.2 – TAP State Control The TAP provides an independent serial channel to communicate synchronously with the host system. The TAP state control is achieved through host manipulation of the Test Mode Select (TMS) and Test Clock (TCK) signals. The TMS signal is sampled at the rising edge of TCK and decoded by the TAP controller to control movement between the TAP states. The TDI input and TDO output are meaningful once the TAP is in a serial shift state (i.e. Shift-IR or Shift-DR). 20.2.
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DS4830A User’s Guide Table 20-3: Instruction Register (IR2:0) Encodings IR2:0 INSTRUCTION FUNCTION SERIAL DATA SHIFT REGISTER SELECTION 000 Extest No operation Unchanged. Retain previous selection 001 Sample/Preload No operation Unchanged.
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DS4830A User’s Guide commands and data can be exchanged between the host and the DS4830A by operating in the data register portion of the state sequence (i.e. DR-Scan). The TAP retains the private instruction which was loaded into IR2:0 until a new instruction is shifted in or until the TAP controller returns to the Test-Logic-Reset state. 20.3.
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DS4830A User’s Guide TCK TMS Test-Logic-Reset Select-IR-Scan Select-DR-Scan Run-Test/Idle Update-DR Exit1-DR Shift-DR Exit2-DR Pause-DR Exit1-DR Shift-DR Capture-DR Select-DR-Scan Run-Test/Idle Control State TDI Shift Register Don’t care or undefined Parallel Output Instruction Register Don’t care or undefined New Data Old Data Data Register Don’t care or undefined TDO Enable TDO Figure 20-4: TAP Controller Debug Mode DR-Scan Example 164
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DS4830A User’s Guide SECTION 21 – IN-CIRCUIT DEBUG MODE The DS4830A is equipped with embedded debug hardware and embedded ROM firmware developed for the purpose of providing in-circuit debugging capability to the user application. The in-circuit debug mode uses the JTAG-compatible Test Access Port (TAP) as its means of communication between the host and the DS4830A. Figure 21-1 shows a block diagram of the in-circuit debugger.
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DS4830A User’s Guide DS4830A 9 9 0 X X Host Command / Data Input TDI 0 TDO s1 DS4830A Data Output s0 Status Figure 21-2: 10-Bit Word Format Table 21-1: Status Bits s1:s0 STATUS/CONDITION 00 Non-Debug. Default condition, Background mode, or debug engine inactive. 01 Debug Idle. Debug engine is ready to receive data from the host (command, data). 10 Debug Busy. Debug engine is busy without valid data (i.e. ROM code execution, trace operations). 11 Debug Valid.
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DS4830A User’s Guide Table 21-2: Background Mode Commands OPCODE COMMAND OPERATION 0000-0000 No Operation No operation. (Default state for Debug Shift register). Read control data from the ICDC. The contents of the ICDC register will be loaded into the Debug 0000-0001 Read ICDC Shift Register via the ICDB register for host read. This command requires one follow-on transfer cycle. Read flags from the ICDF.
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DS4830A User’s Guide 21.1.1.1 – Breakpoint 0 Register (BP0) Bit Name Reset Access 15 14 13 12 11 10 9 1 s 1 s 1 s 1 s 1 s 1 s 1 s 8 7 BP0[15:0] 1 1 s s 6 5 4 3 2 1 0 1 s 1 s 1 s 1 s 1 s 1 s 1 s s = special The Breakpoint 0 register is accessible only via background mode read/write commands. Breakpoint registers BP0, BP1, BP2, and BP3 serve as program memory address breakpoints.
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DS4830A User’s Guide Bit Name Reset Access 15 1 s 14 1 s 13 1 s 12 1 s 11 1 s 10 1 s 9 1 s 8 r.4 1 s 7 r.3 1 s 6 r.2 1 s 5 r.1 1 s 4 r.0 1 s 3 M.3 1 s 2 M.2 1 s 1 M.1 1 s 0 M.0 1 s s = special 21.1.1.6 – Breakpoint 5 Register (BP5) The Breakpoint 5 register is accessible only via background mode read/write commands. When REGE = 0: This register serves as one of the two data memory address breakpoints.
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DS4830A User’s Guide 21.2 – Debug Mode There are two ways to enter the Debug Mode from Background Mode: 1. Issuance of the Debug command directly by the host via the TAP communication port, or 2. Breakpoint matching mechanism. The host can issue the Debug background command to the debug engine. This direct Debug Mode entry is nondeterministic. The response time varies dependent on system conditions when the command is issued.
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DS4830A User’s Guide provide an indication of completion to the host, while others (e.g., Read Register Map) need to supply multiple bytes of output data. To accomplish data flow control between the host and ROM, the status bits should be used by the host to assess when the ROM is ready for additional data and/or when the ROM is providing valid data output. Internally, the ROM can ascertain when new data is available or when it may output the next data byte via the TXC flag.
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DS4830A User’s Guide OPCODE COMMAND 0010-0101 Write data memory 0010-0110 Trace 0010-0111 Return 0010-1000 Unlock password 0010-1001 Read register OPERATION Write data to a selected data memory location. This command requires four followon transfer cycles, two for the memory address and two for the data, starting with the LSB address and ending with the MSB data. The input address must be based memory map when executing from utility ROM, as shown in Figure 2-4.
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DS4830A User’s Guide Table 21-4: Output from Read Register Map Command WO RD REGISTER WO RD 0 PO2 32 1 PO1 33 I2CST_M 65 2 PO0 34 I2CIE_M 3 EIF2 35 4 EIF1 5 WO RD REGISTER 192 A[3] QTCN 193 A[4] 162 LTIL 194 A[5] 163 HTIL 195 A6[] 164 196 A[7] 165 197 A[8] REGISTER WORD REGISTER WORD 96 MCNT 128 ADCN 160 I2CST_S 97 MA 129 SENR 161 66 MPNTR 98 MB 130 ADST PO6 67 I2CTXFST 99 MC2 131 ADST1 36 CRC8IN 68 I2CTXFIE 100 MC1 132 EIF0 37 M
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DS4830A User’s Guide 21.2.4 – Return To terminate the debug mode and return the debug engine to background mode, the host must issue a Return command to the debug engine. This command causes the following actions: 1) 2) 3) 4) 5) Pop the return address from the stack Set the IGE bit to logic 1 if debug mode was activated when IGE=1.
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DS4830A User’s Guide 21.3 – In-Circuit Debug Peripheral Registers The following peripheral registers are used to control the in-circuit debug mode of the DS4830A. Addresses of registers are given as “Mx[yy],” where x is the module number (from 0 to 5 decimal) and yy is the register index (from 00h to 1Fh hexadecimal). Fields in the bit definition tables are defined as follows: ● Name: Symbolic names of bits or bit fields in this register.
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DS4830A User’s Guide 21.3.3 – In-Circuit Debug Control Register (ICDC, M2[1Ah]) Bit Name Reset Access 7 DME 0 rs 6 0 r 5 REGE 0 rs 4 0 r 3 CMD3 0 rs 2 CMD2 0 rs 1 CMD1 0 rs 0 CMD0 0 rs r = read, s = special BIT 7 NAME DME 6 5 Reserved REGE 4 3:0 Reserved CMD3:0 DESCRIPTION Debug Mode Enable (DME). When this bit is cleared to 0, background mode commands may be executed, but breakpoints are disabled.
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DS4830A User’s Guide 21.3.4 – In-Circuit Debug Flag Register (ICDF, M2[1Bh]) Bit Name Reset Access 7 0 r 6 0 r 5 0 r 4 0 r 3 PSS1 0 rw 2 PSS0 0 rw 1 JTAG_SPE 0 rw 0 TXC 0 rw r = read, s = special BIT 7:4 3:2 NAME Reserved PSS[1:0] 1 JTAG_SPE 0 TXC DESCRIPTION Reserved. Do not write to these bits. Programming Source Select Bits [1:0].
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DS4830A User’s Guide 21.3.7 – In-Circuit Debug Data Register (ICDD, M2[1Eh]) Bit Name Reset Access 15 14 13 12 11 10 0 r 0 r 0 r 0 r 0 r 0 r 9 8 7 ICDD[15:0] 0 0 0 r r r 6 5 4 3 2 1 0 0 r 0 r 0 r 0 r 0 r 0 r 0 r This register is used by the debug engine to store data or read count so that ROM code can view that information. This register is also used by the debug engine as a data register for content matching when BP5 is used as a register breakpoint.
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DS4830A User’s Guide SECTION 22 – IN-SYSTEM PROGRAMMING The DS4830A contains an internal bootstrap loader utilizing the JTAG or I2C interfaces. As a result, system software can be upgraded in-system, eliminating the need for a costly hardware retrofit when software updates are required. After each device reset, DS4830A ROM code is executed which determines if bootloader operation is desired. Figure 22-1 provides information on how the DS4830A enters into bootloader operation.
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DS4830A User’s Guide 22.1.1 – Password Protection The DS4830A uses a password to protect the contents of the program memory from simple access and viewing. The password resides in the 32 bytes of program memory at byte address 0020h through 003Fh. A valid password is defined as any value that does not contain all 0000h or FFFFh. Following a reset, the Password Lock Bit (PWL) in the SC register will be set if the DS4830A contains a valid password.
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DS4830A User’s Guide Table 22-2: JTAG Bootloader Status Bits BITS 1:0 STATUS 00 Reserved 01 Reserved 10 Loader-Busy 11 Loader-Valid CONDITION Invalid condition. Invalid condition ROM Loader is busy executing code or processing the current command. ROM Loader is supplying valid output data to the host in current shift operation. 22.1.3 – Entering I2C Bootloader The DS4830A also has built-in functionality that allows bootloading over I2C.
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DS4830A User’s Guide 22.2 – Bootloader Operation Once in bootloader mode, the JTAG and I2C interfaces both use the same commands. How these commands are implemented will be different between the two interfaces. Table 22-4 shows an example command and parameters. The next two sections will detail how to implement these commands using either the JTAG or I2C interface.
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DS4830A User’s Guide 22.2.2 – I2C Bootloader Protocol After entering the I2C bootloader, all I2C communication takes place on the default I2C bootloader slave address 36h. When writing data to the DS4830A, slave address 36h (R/W bit = 0) is used. To read data from the DS4830A I2C bootloader, slave address 37h (R/W bit = 1) is used. The I2C bootloader does not return the status bits that are available from the JTAG bootloader.
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DS4830A User’s Guide 22.3 – Bootloader Commands Commands for the DS4830A loader are grouped into families. All bootloader commands begin with a single command byte. The upper four bits of this command byte define the command family (from 0 to 15), while the lower four bits define the specific command within that family. The loader command families are shown in Table 22-5.
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DS4830A User’s Guide 22.3.4 – Command 03h – Password Match Byte 1 Bytes 2 to 33 Command Data In 03h 32-Byte Password Input X X Output Byte 34 NOP 00h X Byte 35 Return 00h 3Eh This command accepts a 32-byte password value, which is matched against the password in program memory from byte address 0020h through 003Fh. If the entered value matches the password in program memory, the password lock bit will be cleared. This command is not password protected. 22.3.
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DS4830A User’s Guide 22.3.6 – Command 05h – Get Supported Commands Byte 1 Byte 2 Byte 3 Command NOP Data Out 05h 00h 00h Input X X SupportL Output Byte 4 Data Out 00h SupportH Byte 5 Data Out 00h 00h Byte 6 Data Out 00h 00h Byte 7 Return 00h 3Eh The SupportL (LSB) and SupportH (MSB) bytes form a 16-bit value that indicates which command families the bootloader supports. If bit 0 is set to 1, it indicates that Family 0 is supported. If bit 1 is set to 1, it indicates that Family 1 is supported.
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DS4830A User’s Guide 22.3.11 – Command 10h – Load Code Byte 1 Byte 2 Input Output Command 10h X Data In Length X Byte 3 Byte 4 Data In AddressL X Data In AddressH X (Length) Bytes Data In Data to load X Byte Length+5 NOP 00h X Byte Length+6 Return 00h 3Eh This command programs (Length) bytes of data into the program flash starting at byte address (AddressH:AddressL). The bootloader writes one 16-bit word to flash at a time.
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DS4830A User’s Guide 22.3.14 – Command 21h – Dump Data Byte 1 Byte 2 Byte 3 Input Output Command 21h X Data In 2 X Data In AddrL X Byte 4 Byte 5 Byte 5 Byte 6 Data In AddrH X Data In LengthL X Data In LengthH X NOP 00h X Length Bytes Data Out 00h Memory Byte Length+7 Return 00h 3Eh This command returns the contents of the SRAM memory. The memory dump begins at byte address AddrH:AddrL and will contain LengthH:LengthL bytes. This command is password protected. 22.3.
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DS4830A User’s Guide 22.3.17 – Command 40h – Verify Code Byte 1 Byte 2 Byte 3 Byte 4 (Length) Bytes Command 40h X Data In AddrL X Data In AddrH X Data In Data to Verify X Input Output Data In Length X Byte Length+5 NOP 00h X Byte Length+6 Return 00h 3Eh This command operates in the same manner as the Load Code command, except that instead of programming the input data into flash memory, it verifies that the input data matches the data already in code space.
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DS4830A User’s Guide SECTION 23 – PROGRAMMING The following section provides a programming overview of the DS4830A. For full details on the instruction set, as well as System Register and Peripheral Register detailed bit descriptions, see the appropriate sections in this user’s guide. 23.1 – Addressing Modes The instruction set for the DS4830A provides three different addressing modes: direct, indirect and immediate.
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DS4830A User’s Guide 23.3 – Reading and Writing Registers All functions in the DS4830A are accessed through registers, either directly or indirectly. This section discusses loading registers with immediate values and transferring values between registers of the same size and different sizes. 23.3.
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DS4830A User’s Guide move GR, LC[0] move IC, GRH ; move LC[0] to the GR register ; copy the high byte into the IC register 16-Bit Destination  Concatenation (8-Bit Source, 8-Bit Source) Two 8-bit source registers can be concatenated and stored into a 16-bit destination by using the prefix register to hold the high order byte for the concatenated transfer. An additional cycle may be required if either source byte register index is greater than 0Fh.
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DS4830A User’s Guide Register bits may be set or cleared individually using the MOVE instruction as follows. move IGE, #1 move APC.6, #0 ; set IGE (Interrupt Global Enable) bit ; clear IDS bit (APC.6) As with other instructions, prefixing is required to select destination registers beyond index 07h. The MOVE instruction may also be used to transfer any one of the lowest 8 bits from a register source or any bit of the active accumulator (Acc) to the Carry flag.
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DS4830A User’s Guide • • • • • MOVE Acc, src MOVE dst, Acc MOVE Acc, Acc XCHN XCH (Copy data from source to active accumulator) (Copy data from active accumulator to destination) (Recirculation of active accumulator contents) (Exchange nibbles within each byte of active accumulator) (Exchange active accumulator bytes) The active accumulator may not be the source in any instruction where it is also the implicit destination.
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DS4830A User’s Guide 23.5.3 – ALU Operations Using the Active Accumulator and a Source The following arithmetic and logical operations can use any register or immediate value as a source. The active accumulator Acc is always used as the second operand and the implicit destination. Also, Acc may not be used as the source for any of these operations.
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DS4830A User’s Guide Since the Sign flag is a dynamic reflection of the high bit of the active accumulator, any instruction that changes the value in the active accumulator can potentially change the value of the Sign flag. Also, any instruction that changes which accumulator is the active one (including AP auto-increment/decrement) can also change the Sign flag. The following operation uses the Sign flag: JUMP S, src ; Jump if Sign flag is set 23.6.2 – Zero Flag The Zero flag (PSF.
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DS4830A User’s Guide • • • XOR Acc. JUMP C, src JUMP NC, src (Carry = Carry XOR selected active accumulator bit) (Jump if Carry flag is set) (Jump if Carry flag is cleared) 23.6.5 – Overflow Flag The Overflow flag (PSF.2) is a static flag indicating that the carry or borrow bit (Carry status Flag) resulting from the last ADD/ADDC or SUB/SUBB operation but did not match the carry or borrow of the high order bit of the active accumulator.
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DS4830A User’s Guide 23.7.3 – Conditional Jumps Conditional jumps transfer program execution based on the value of one of the status flags (C, E, Z, S). Except where noted for JUMP E and JUMP NE, the absolute and relative operands allowed are the same as for the unconditional JUMP command.
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DS4830A User’s Guide If opting to preload the loop address to an internal 16-bit register, the most time and code efficient means is by performing the load in the instruction just prior to the top of the loop: move LC[1], #10h move LC[0], IP LoopTop: ... ; Set loop counter to 16 ; Set loop address to the next address ; loop addr not relative to djnz LC[n],src 23.7.6 – Conditional Returns Similar to the conditional jumps, the DS4830A microcontroller also supports a set of conditional return operations.
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DS4830A User’s Guide ... (interrupt servicing code) ... pop IMR ret ; restore previous interrupt mask ; back to code or lower priority interrupt Note that configuring a given IMR register mask bit to '0' only prevents interrupt conditions from the corresponding module or system from generating an interrupt request. Configuring an IMR mask bit to '0' does not prevent the corresponding IIR system or module identification flag from being set.
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DS4830A User’s Guide Since the stack is 16 bits wide, it is possible to store two 8-bit register values on it in a single location. This allows more efficient use of the stack if it is being used to save and restore registers at the start and end of a subroutine. SubOne: move PFX[0], IC push PSF ... pop GR move IC, GRH move PSF, GRL ret ; store IC:PSF on the stack ; 16-bit register ; IC was stored as high byte ; PSF was stored as low byte 23.
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DS4830A User’s Guide select bits (SDPS1:0; DPC.1:0), or implicitly by writing to the DP[n], BP or OFFS registers. Any indirect memory write operation using a data pointer will set the SDPS bits, thus activating the write pointer as the active source pointer.
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DS4830A User’s Guide SECTION 24 – INSTRUCTION SET Table 24-1. Instruction Set Summary DATA TRANSFER BRANCHING MATH BIT OPERATIONS LOGICAL OPERATIONS MNEMONIC AND src OR src XOR src CPL NEG SLA SLA2 SLA4 RL RLC SRA SRA2 SRA4 SR RR RRC MOVE C, Acc. MOVE C, #0 MOVE C, #1 CPL C MOVE Acc., C AND Acc. OR Acc. XOR Acc. MOVE dst., #1 MOVE dst., #0 MOVE C, src.
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DS4830A User’s Guide Note 4: Any index represented by or found inside [ ] brackets is considered variable, but required. Note 5: The active accumulator (Acc) is not allowed as the dst if A[AP] is specified as the src. Note 6: The '{L/S}' prefix is optional. Note 7: Instructions that attempt to simultaneously push/pop the stack (e.g. PUSH @SP--, PUSH @SPI--, POP @++SP, POPI @++SP) or modify SP in a conflicting manner (e.g., MOVE SP, @SP--) are invalid.
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DS4830A User’s Guide AND src Logical AND Description: Performs a logical-AND between the active accumulator (Acc) and the specified src data. For the complete list of src specifiers, reference the MOVE instruction. Because the source field is limited to 8 bits, the PFX[n] register is used to supply the high-byte of data for 16 bit sources.
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DS4830A User’s Guide {L/S}CALL src {Long/Short} Call to Subroutine Description: Performs a call to the subroutine destination specified by src. The CALL instruction uses an 8-bit immediate src to perform a relative short call (IP +127/-128 words). The CALL instruction uses a 16-bit immediate src to perform an absolute long CALL to the specified 16-bit address. The PFX[0] register is used to supply the high byte of a 16-bit immediate address for the absolute long CALL. Using the optional ‘L’ prefix (i.e.
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DS4830A User’s Guide CMP src Compare Accumulator Description: Compare for equality between the active accumulator and the least significant byte of the specified src. Because the source is limited to 8 bits, the PFX[n] register is used to supply the high-byte of data for 16 bit sources.
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DS4830A User’s Guide {L/S}DJNZ LC[n], src Decrement Counter, {Long/Short} Jump Not Zero Description: The DJNZ LC[n], src instruction performs a conditional branch based upon the associated Loop Counter (LC[n]) register. The DJNZ LC[n], src instruction decrements the LC[n] loop counter and branches to the address defined by src if the decremented counter has not reached 0000h.
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DS4830A User’s Guide {L/S} JUMP src Unconditional {Long/Short} Jump Description: Performs an unconditional jump as determined by the src specifier. The JUMP instruction uses an 8-bit immediate src to perform a relative jump (IP +127/-128 words). The JUMP instruction uses a 16-bit immediate src to perform an absolute JUMP to the specified 16-bit address. The PFX[0] register is used to supply the high byte of a 16-bit immediate address for the absolute JUMP. Using the optional ‘L’ prefix (i.e.
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DS4830A User’s Guide {L/S} JUMP C / {L/S} JUMP NC, src {L/S} JUMP Z / {L/S} JUMP NZ, src {L/S} JUMP E / {L/S} JUMP NE, src {L/S} JUMP S, src Conditional {Long/Short} Jump on Status Flag Description: Performs conditional branching based upon the state of a specific processor status flag. JUMP C results in a branch if the Carry flag is set while JUMP NC branches if the Carry flag is clear. JUMP Z results in a branch if the Zero flag is set while JUMP NZ branches if the Zero flag is clear.
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DS4830A User’s Guide JUMP NZ Operation: Encoding: Example(s): JUMP E Operation: Encoding: Example(s): Z=0: IP  IP + src (relative) –or— src (absolute) Z=1: IP  IP + 1 15 f101 0 1100 ssss JUMP NZ, label1 ssss ; Z=1, branch not taken E=1: IP  IP + src (relative) –or— src (absolute) E=0: IP  IP + 1 15 0011 0 1100 ssss JUMP E, label1 ssss ; E=1, branch taken Special Notes: The src specifier must be immediate data.
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DS4830A User’s Guide MOVE dst, src Move Data Description: Moves data from a specified source (src) to a specified destination (dst). A list of defined source, destination specifiers is given in the table below. Also, since src can be either 8-bit (byte) or 16-bit (word) data, the rules governing data transfer are also explained below in the encoding section.
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DS4830A User’s Guide MOVE dst, src (continued) Destinati on Specifier Codesdst dst Bit Encoding ddd dddd NUL 111 0110 MN[n] nnn 0NNN AP APC PSF IC IMR A[n] Acc PFX[n] @++SP SP IV LC[n] @BP[Offs] @BP[++Offs] @BP[--Offs] OFFS DPC GR GRL BP @DP[n] @++DP[n] @--DP[n] DP[n] 000 1000 001 1000 100 1000 101 1000 110 1000 nnn 1001 000 1010 nnn 1011 000 1101 001 1101 010 1101 11n 1101 000 1110 001 1110 010 1110 011 1110 100 1110 101 1110 110 1110 111 1110 n00 1111 n01 1111 n10 1111 n11 1111 16 or 8 Bits 8/16
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DS4830A User’s Guide Example(s): ; A[0]  A[3] ; DP[0]  #0110h (PFX[0] register used) ; MOVE PFX[0], #01h (smart-prefixing) ; MOVE DP[0], #10h ; DP[0]  #0080h (PFX[0] register not needed) MOVE A[0], A[3] MOVE DP[0], #110h MOVE DP[0], #80h Special Notes: Proper loading of the PFX[n] registers, when for the purpose of supplying 16-bit immediate data or accessing 2-cycle destinations, is handled automatically by the assembler and is therefore an optional step for the user when writing assembly source cod
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DS4830A User’s Guide MOVE C, Acc. Move Accumulator Bit to Carry Flag Description: Replaces the Carry (C) status flag with the specified active accumulator bit. Status Flag: C Operation: C  Acc. Encoding: 15 1110 0 1010 bbbb Example(s): 1010 ; Acc = 01C0h, C=0 ; C =1 MOVE C, Acc.8 MOVE C, src. Move Bit to Carry Flag Description: Replaces the Carry (C) status flag with the specified source bit src.. Status Flag: C Operation: C  src.
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DS4830A User’s Guide MOVE C, #1 Set Carry Flag Description: Sets the Carry (C) processor status flag. Status Flags: C1 Operation: C1 Encoding: 15 1101 0 1010 0001 Example(s): 1010 ;C=0 ;C1 MOVE C, #1 MOVE dst., #0 Clear Bit Description: Clears the bit specified by dst.. Status Flags: C, E (if dst is PSF) Operation: dst.  0 Encoding: 15 1ddd 0 dddd 0bbb Example(s): MOVE M0[0].1, #0 MOVE M0[0].
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DS4830A User’s Guide NEG Negate Accumulator Description: Performs a negation (two’s complement) of the active accumulator and returns the result back to the active accumulator. Status Flags: S, Z Operation: Acc  ~Acc + 1 Encoding: 15 1000 0 1010 1001 Example(s): 1010 ; Acc = FEEDh, S=1, Z=0 ; Acc = 0113h, S=0, Z=0 NEG OR src Logical OR Description: Performs a logical-OR between the active accumulator (Acc or A[AP]) and the specified src data.
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DS4830A User’s Guide POP dst Pop Word from the Stack Description: Pops a single word from the stack (@SP) to the specified dst and decrements the stack pointer (SP).
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DS4830A User’s Guide PUSH src Push Word to the Stack Description: (@SP).
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DS4830A User’s Guide RET C / RET NC RET Z / RET NZ RET S Conditional Return on Status Flag Description: Performs conditional return (RET) based upon the state of a specific processor status flag. RET C returns if the Carry flag is set while RET NC returns if the Carry flag is clear. RET Z returns if the Zero flag is set while RET NZ returns if the Zero flag is clear. RET S returns if the Sign flag is set. See RET for additional information on the return operation.
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DS4830A User’s Guide RETI Return from Interrupt Description: RETI pops a single word from the stack (@SP) into the Instruction Pointer (IP) and decrements the stack pointer (SP). Additionally, RETI returns the interrupt logic to a state in which it can acknowledge additional interrupts.
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DS4830A User’s Guide RETI Z Operation: Encoding: Example(s): RETI NZ Operation: Encoding: Example(s): RETI S Operation: Encoding: Example(s): Z=1: IP  @SP-INS 0 Z=0: IP  IP + 1 15 1001 0 1100 1000 RETI Z 1101 ; Z=0, return from interrupt (RETI) does not occur Z=0: IP  @SP-INS 0 Z=1: IP  IP + 1 15 1101 0 1100 1000 RETI NZ 1101 ; Z=0, return from interrupt (RETI) is performed S=1: IP  @SP-INS 0 S=0: IP  IP + 1 15 1100 RETI S 0 1100 1000 1101 ; S=0, return from interrupt (RETI) d
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DS4830A User’s Guide RL / RLC Rotate Left Accumulator Carry Flag (Ex/In)clusive Description: Rotates the active accumulator left by a single bit position. The RL instruction circulates the msb of the accumulator (bit 15) back to the lsb (bit 0) while the RLC instruction includes the Carry (C) flag in the circular left shift. Status Flags: C (for RLC only), S, Z (for RLC only) RL Operation: 15 Active Accumulator (Acc) 0 Acc.[15:1] Acc.[14:0]; Acc.0  Acc.
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DS4830A User’s Guide RR / RRC Rotate Right Accumulator Carry Flag (Ex/In)clusive Description: Rotates the active accumulator right by a single bit position. The RR instruction circulates the lsb of the accumulator (bit 0) back to the msb (bit 15) while the RRC instruction includes the Carry (C) flag in the circular right shift. Status Flags: C (for RRC only), S, Z (for RRC only) RR Operation: 15 Active Accumulator (Acc) 0 Acc.[14:0] Acc.[15:1]; Acc.15  Acc.
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DS4830A User’s Guide SLA / SLA2 / SLA4 Shift Accumulator Left Arithmetically One, Two, or Four Times Description: Shifts the active accumulator left once, twice, or four times respectively for SLA, SLA2, and SLA4. For each shift iteration, a ‘0’ is shifted into the lsb and the msb is shifted into the Carry (C) flag. For signed data, this shifting process effectively retains the sign orientation of the data to the point at which overflow/underflow would occur.
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DS4830A User’s Guide SR SRA / SRA2 / SRA4 Shift Accumulator Right Shift Accumulator Right Arithmetically One, Two, or Four Times Description: Shifts the active accumulator right once for the SR, SRA instructions and 2 or 4 times respectively for the SRA2, SRA4 instructions. The SR instruction shifts a 0 into the accumulator msb while the SRA, SRA2, and SRA4 instructions effectively shift a copy of the current msb into the accumulator, thereby preserving any sign orientation.
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DS4830A User’s Guide SRA2 Operation: 15 Active Accumulator (Acc) 0 Carry Flag 0 Carry Flag Acc.[13:0] Acc.[15:2] Acc.[15:14]  Acc.15 C  Acc.1 Encoding: 15 1000 0 1010 1110 Example(s): ; Acc = 0003h, C=0, Z=0 ; Acc = 0000h, C=1, Z=1 SRA2 SRA4 Operation: 1010 15 Active Accumulator (Acc) Acc.[11:0] Acc.[15:4] Acc.[15:12]  Acc.15 C  Acc.
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DS4830A User’s Guide SUB / SUBB src Subtract / Subtract with Borrow Description: Subtracts the specified src from the active accumulator (Acc) and returns the result back to the active accumulator. The SUBB additionally subtracts the borrow (Carry Flag) which may have resulted from previous subtraction. For the complete list of src specifiers, reference the MOVE instruction. Because the source is limited to 8 bits, the PFX[n] register is used to supply the high-byte of data for 16 bit sources.
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DS4830A User’s Guide XCH Exchange Accumulator Bytes Description: Exchanges the upper and lower bytes of the active accumulator. Status Flags: S Operation: Acc.[15:8]  Acc.[7:0] Acc.[7:0]  Acc.[15:8] Encoding: 15 1000 0 1010 1000 Example(s): 1010 ; Acc = 2345h ; Acc = 4523h XCH XCHN Exchange Accumulator Nibbles Description: Status Flags: Exchanges the upper and lower nibbles in the active accumulator byte(s). S Operation: Acc.[7:4]  Acc.[3:0] Acc.[3:0]  Acc.[7:4] Acc.[15:12]  Acc.
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DS4830A User’s Guide XOR src Logical XOR Description: Performs a logical-XOR between the active accumulator (Acc or A[AP]) and the specified src data. For the complete list of src specifiers, reference the MOVE instruction. Because the source is limited to 8 bits, the PFX[n] register is used to supply the high-byte of data for 16 bit sources.
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DS4830A User’s Guide SECTION 25 – UTILITY ROM 25.1 – Overview The DS4830A utility ROM includes routines that provide the following functions to application software: • In-application programming routines for flash memory (program, erase, mass erase) • Single word/byte copy and buffer copy routines for lookup tables in flash To provide backwards compatibility among different versions of the utility ROM, a function address table is included that contains the entry points for all user-callable functions.
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DS4830A User’s Guide 25.2 – In-Application Programming Functions 25.2.1 – UROM_flashWrite Function UROM_flashWrite Summary Programs a single word of flash memory Inputs Outputs A[0]: Word address in program flash memory to write. A[1]: Value to write to flash memory. Carry: Set on error and cleared on success Destroys PSF, LC[1] Notes: • This function uses two stack levels to save and restore values. • If the watchdog reset function is active, it should be disabled before calling this function.
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DS4830A User’s Guide 25.3 – Data Transfer Functions The DS4830A cannot access data from the same memory segment that is currently being used for instructions. For example, when instructions are executing from FLASH, data in FLASH cannot be accessed. The following utility ROM functions can be used to transfer data from one memory segment to another. For example, if data in FLASH needs to be copied to SRAM, one of these ROM functions can be called to do this transfer.
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DS4830A User’s Guide 25.3.3 – UROM_moveDP0dec Function UROM_moveDP0dec Summary Reads the byte/word value pointed to by DP[0], then decrements DP[0]. Inputs DP[0]: Address to read from data space (include 8000h offset if reading from flash). Outputs GR: Data byte/word read. DP[0] is decremented. Destroys None Notes: • Before calling this function, DPC should be set appropriately to configure DP[0] for byte or word mode.
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DS4830A User’s Guide 25.3.6 – UROM_moveDP1dec Function UROM_moveDP1dec Summary Reads the byte/word value pointed to by DP[1], then decrements DP[1]. Inputs DP[1]: Address to read from data space (include 8000h offset if reading from flash). Outputs GR: Data byte/word read. DP[1] is decremented. Destroys None Notes: • Before calling this function, DPC should be set appropriately to configure DP[1] for byte or word mode.
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DS4830A User’s Guide 25.3.9 – UROM_moveBPdec Function UROM_moveBPdec Summary Reads the byte/word value pointed to by BP[OFFS], then decrements OFFS. Inputs BP[OFFS]: Address to read from data space (include 8000h offset if reading from flash). Outputs GR: Data byte/word read. OFFS is decremented. Destroys None Notes: • Before calling this function, DPC should be set appropriately to configure BP[OFFS] for byte or word mode.
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DS4830A User’s Guide 25.4 Special Functions The DS4830A provides software reset and read single word functions. 25.4. 1 – UROM_copyWord Function UROM_copyWord Summary 1 word DP[0] to A[0]. Inputs DP[0]: Starting address to copy from. Outputs A[0] Destroys A[0], DP[0] UROM 885Bh Address Notes: • This function can be used to copy a word from program flash to data RAM, or from one part of data RAM to another.
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DS4830A User’s Guide 25.5 – Utility ROM Examples 25.5.
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DS4830A User’s Guide SECTION 26 – MISCELLANEOUS 26.1 – Overview Miscellaneous features of DS4830A are • CRC8 • Software interrupts • General-purpose registers. 26.2 – CRC8 DS4830A has an built-in hardware CRC8. The registers used for CRC8 are CRC8IN and CRC8OUT. They are defined in Module 1. SMBus 2.0 specification is followed for CRC algorithm (CRC polynomial is x8+x2+x+1). 26.2.
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DS4830A User’s Guide 26.3.1 – User Interrupt Register (USER_INT) Bit Name Reset Access 7 SW_F3 0 rw BIT 7:4 NAME SW_F3[3:0] 3:0 SW_INT[3:0] 6 SW_F2 0 rw 5 SW_F1 0 rw 4 SW_F0 0 rw 3 SW_INT4 0 rw 2 SW_INT 3 0 rw 1 SW_INT 2 0 rw 0 SW_INT 1 0 rw DESCRIPTION Software flags: Single cycle read/write bits for general-purpose flags for application usage. Software Interrupt: Setting this bit to ‘1’ generates an interrupt. 26.