Owner manual
DS4830 User’s Guide
95
11.2 – I2C Slave Controller Register Description
Following are the registers that are used to control the I
2
C Slave Interface, which is the SDA and SCL pins. These
registers are used to control the I
2
C slave interface if it is operating as either a slave or master. The bit descriptions below
detail how to use these registers when operating in slave mode. When operating in master mode, some of the bits and
registers have different functionality. See the I
2
C Master Interface for more information on how to control the I
2
C Slave
Interface when it is operating as a master.
11.2.1 – I
2
C Slave Control Register (I2CCN_S)
Address: M2[0Ch]
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
-
-
-
-
-
SMB_MOD
I2CSTREN
I2CGCEN
I2CSTOP
I2CSTART
I2CACK
I2CSTRS
-
-
I2CMST
I2CEN
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Access
r
r
r
r
r
r
rw*
rw*
r
r
rw*
rw*
r
r
r
rw*
* Unrestricted Read. Unrestricted write access when I2CBUSY=0. Writes to I2CEN are disabled when I2CBUSY=1.
BIT
NAME
DESCRIPTION
15:11
Reserved
Reserved. The user should write 0 to these bits.
10
SMB_MOD
Slave SMBUS Mode Operation. When this bit is set to a ‘1’, SMBus timeout functionality is enabled for the
I
2
C slave interface. When this bit is cleared to ‘0’, the SMBus timeout functionality is disabled. See the
SMBus Timeout section for more details.
9
I2CSTREN
I
2
C Slave Clock Stretch Enable. Setting this bit to '1' will stretch the clock (holds SCL low) at the end of the
clock cycle specified in I2CSTRS. Clearing this bit disables clock stretching.
8
I2CGCEN
I
2
C Slave General Call Enable. Setting this bit to '1' will enable the I
2
C to respond to a general call address
(address = 0000 0000). Clearing this bit to '0' will disable response to general call address.
7
I2CSTOP
This bit has no function when operating in slave mode.
6
I2CSTART
This bit has no function when operating in slave mode.
5
I2CACK
I
2
C Slave Data Acknowledge Bit. This bit selects the acknowledge bit returned by the I
2
C controller while
acting as a receiver. Setting this bit to ‘1’ will generate a NACK (leaving SDA high). Clearing the I2CACK bit
to ‘0’ will generate an ACK (pulling SDA LOW) during the acknowledgement cycle. This bit will retain its
value unless changed by software or hardware.
4
I2CSTRS
I
2
C Slave Clock Stretch Select. Setting this bit to ‘1’ will enable clock stretching after the falling edge of the
8
th
clock cycle. Clearing this bit to ‘0’ will enable clock stretching after the falling edge of the 9
th
clock cycle.
This bit has no effect when clock stretching is disabled (I2CSTREN=0).
3:2
Reserved
Reserved. The user should write 0 to these bits.
1
I2CMST
I
2
C Master Mode Enable. Setting this bit to ‘1’ will enable I
2
C master functionality on the SDA and SCL
pins. See the I
2
C Master Interface section for more details. Setting this bit to ‘0’ enables I
2
C slave
functionality.
0
I2CEN
I
2
C Slave Enable. This bit enables the I
2
C Slave function. When set to ’1’, I
2
C Slave communication is
enabled. When cleared to ‘0’, the I
2
C function is disabled.