Owner manual

DS4830 User’s Guide
22
2.6.4 – Internal System Resets
There are two possible sources of internal system resets. An internal reset will hold the DS4830 in reset mode for 12
clock cycles.
1. When data BBh is written to the special I
2
C slave address 34h.
2. When in-system programming is complete and the ROD bit is set to 1.
2.7 – Clock Generation
The DS4830 generates its 20MHz peripheral clock using an internal oscillator and generates 10MHz instruction clock by
divide 2.This oscillator will startup when V
DD
exceeds the brownout voltage level, V
BO
. There is a delay of approximately
1msec between when the oscillator starts and when clocking of the DS4830 begins. This delay ensures that the clock is
stable prior to beginning normal operation.