Owner manual

DS4830 User’s Guide
153
For the host to establish a specific data communication link, a private instruction must be loaded into the IR2:0 register.
Once the instruction is latched in the instruction parallel buffer at the Update-IR state, it is recognized by the TAP
controller and the communication channel is established. In-Circuit Debug or In-System Programming commands and
data can be exchanged between the host and the DS4830 by operating in the data register portion of the state sequence
(i.e. DR-Scan). The TAP retains the private instruction which was loaded into IR2:0 until a new instruction is shifted in or
until the TAP controller returns to the Test-Logic-Reset state.
20.3.1 - TAP Communication Examples – IR-Scan and DR-Scan
Figures 20-3 and 20-4 below illustrate examples of communication between the host JTAG controller and the Test Access
Port (TAP) of the DS4830. The host controls the TCK and TMS signals to move through the desired TAP states while
accessing the selected shift register through the TDI input and TDO output pair.
Figure 20-3: TAP Controller Debug Mode IR-Scan Example
Run-Test/Idle
Update-IR
Exit1-IR
Pause-IR
Exit2-IR
Shift-IR
Exit1-IR
Select-DR-Scan
New Instruction
Instruction Register
Test-Logic-Reset
TCK
TMS
TDI
TDO
Control
State
IR Shift
Register
IR Parallel
Output
Register
Selected
TDO
Enable
Capture-IR
Shift-IR
Select-IR-Scan
Run-Test/Idle
By-Pass
Don’t care or undefinedDon’t care or undefined
Don’t care or undefined Don’t care or undefined