Datasheet

DS4432
Dual-Channel, I
2
C, 7-Bit Sink/Source
Current DAC
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Note 1: All voltages with respect to ground. Currents entering the IC are specified positive, and currents exiting the IC are negative.
Note 2: Input resistors (R
FS
) must be between the specified values to ensure the device meets its accuracy and linearity specifications.
Note 3: Supply current specified with all outputs set to zero current setting. SDA and SCL are connected to V
CC
. Excludes current
through R
FS
resistors (I
RFS
). Total current including I
RFS
is I
CC
+ (2 x I
RFS
).
Note 4: The output voltage range must be satisfied to ensure the device meets its accuracy and linearity specifications.
Note 5: Temperature drift excludes drift caused by external resistor.
Note 6: Differential linearity is defined as the difference between the expected incremental current increase with respect to position
and the actual increase. The expected incremental increase is the full-scale range divided by 127.
Note 7: Guaranteed by design.
Note 8: Integral linearity is defined as the difference between the expected value as a function of the setting and the actual value.
The expected value is a straight line between the zero and the full-scale values proportional to the setting.
Note 9: Timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I
2
C standard-mode timing.
Note 10: C
B
—total capacitance of one bus line in pF.
OUTPUT CURRENT SOURCE CHARACTERISTICS (continued)
(V
CC
= +2.7V to +5.5V, T
A
= -40°C to +85°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC source, V
OUT
measured at 1.2V 0.41
Output Current Variation Due to
Power-Supply Change
DC sink, V
OUT
measured at 1.2V 0.41
%/V
DC source, V
CC
= 3.3V 0.08
Output Current Variation Due to
Output-Voltage Change
DC sink, V
CC
= 3.3V 0.14
%/V
Output Leakage Current at Zero
Current Setting
I
ZERO
-1 +1 μA
Output Current Differential
Linearity
DNL (Notes 6, 7) -0.5 +0.5 LSB
Output Current Integral Linearity INL (Notes 7, 8) -1 +1 LSB
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +2.7V to +5.5V, T
A
= -40°C to +85°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCL Clock Frequency f
SCL
(Note 9) 0 400 kHz
Bus Free Time Between STOP
and START Conditions
t
BUF
1.3 μs
Hold Time (Repeated) START
Condition
t
HD:STA
0.6 μs
Low Period of SCL t
LOW
1.3 μs
High Period of SCL t
HIGH
0.6 μs
Data Hold Time t
HD:DAT
0 0.9 μs
Data Setup Time t
SU:DAT
100 ns
START Setup Time t
SU:STA
0.6 μs
SDA and SCL Rise Time t
R
(Note 10) 20 + 0.1C
B
300 ns
SDA and SCL Fall Time t
F
(Note 10) 20 + 0.1C
B
300 ns
STOP Setup Time t
SU:STO
0.6 μs
SDA and SCL Capacitive
Loading
C
B
(Note 10) 400 pF