Datasheet

DS4100H
100MHz HCSL Clock Oscillator
_______________________________________________________________________________________ 5
Pin Description
PIN NAME FUNCTION
1 OE
Output Enable. On-chip pullup resistor. If connected to logic-high or left open, the clock output is
enabled. If connected to logic-low, the output is three-stated.
2 RREF Connect a 475 ±1% resistor from RREF to ground.
3 GND Ground
4 OUTP Positive Clock Output. Requires a series resistor and a pulldown resistor.
5 OUTN Negative Clock Output. Requires a series resistor and a pulldown resister.
6 V
CC
+3.3V Supply Input. Device power can range from 3.135V to 3.465V.
7–10 N.C. No Connection
— EP Exposed Paddle. Do not connect this pad or place exposed metal under the pad.
OUTPUT
BUFFER
RECEIVER
R
S
Z0
CL
Z0 = 50Ω, 35in LENGTH
R
T
R
T
R
T
= 50Ω
R
S
OUTP
OUTN
R
S
= 0Ω FOR TEST, 0 TO 33Ω TO MINIMIZE RINGING IN APPLICATION.
CL = SIMULATES RECEIVER INPUT CAPACITANCE FOR TEST ONLY.
OUTP
OUTN
Z0
CL
CL = 2pF
Figure 2. Typical Termination for HCSL Driver and Test Conditions
OE
OUTP
t
PZH
t
PZ
0.7 x V
CC
0.3 x V
CC
GND
GND
OUTN
t
PZL
Figure 3. HCSL Output Timing Diagram When OE is Enabled and Disabled