Datasheet

DS4100H
100MHz HCSL Clock Oscillator
_______________________________________________________________________________________ 3
Note 1: All voltages are referenced to ground.
Note 2: With 50Ω load to ground on each output pin.
Note 3: Guaranteed by design and not production tested.
Note 4: t
PZL
is defined as the time at which VOE = 1.0V on the rising edge of OE to the time at which V
OUTP
or V
OUTN
= 0.1V
OH
on
the falling edge of OUTP or OUTN.
Note 5: t
PZH
is defined as the time at which the voltage on the rising edge of OE is equal to 1.0V to the time at which V
OUTP
or
V
OUTN
= 0.9V
OH
on the rising edge of V
OUTP
or V
OUTN
.
Note 6: t
PZ
is defined as the time at which VOE = 1.0V on the falling edge of OE to the time at which both V
OUTP
and V
OUTN
are
less than 0.1V
OH
.
Note 7: Frequency stability is calculated as: Δf
TOTAL
= Δf
TEMP
+ Δf
VCC
x 0.165 + Δf
LOAD
+ Δf
AGING
.
Note 8: Measured with 50mV
P-P
sinusoidal signal on the supply from 10kHz to 1MHz.
Note 9: Including oscillator startup time and PLL acquisition time measured after V
CC
reaches 3.0V from power-on.
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 3.135V to 3.465V, T
A
= -40°C to +85°C. Typical values are at V
CC
= +3.3V and T
A
= +25°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Disable Time t
PZ
Figure 3 (Note 6) 10 ns
CLOCK OUTPUT AS MEASURED AT OUTP WITH RESPECT TO OUTN
Clock Output
f
OUT
100 MHz
Frequency Stability
Total
f / f
O
Over temperature range, aging, load, and supply (Note 7) -39 +39 ppm
Initial Frequency
Tolerance
f
_TOL
V
CC
= 3.3V, T
A
= +25°C ±15 ppm
Frequency Stability
vs. Temperature
f / f
O
| T
A
V
CC
= 3.3V -30 +30 ppm
Frequency Stability
vs. V
CC
f / f
O
| V V
CC
= 3.3V ±5% -3 +3 ppm/V
Frequency Stability
vs. Load
f / f
O
| LOAD
±10% variation in termination resistance ±1 ppm
Aging (10 Years) f
AGING
-7 +7 ppm
Phase Jitter (RMS) PJ
RMS
12kHz to 20MHz 0.9 ps
10kHz 3.0
100kHz 27
200kHz 15
Accumulated
Deterministic Jitter Due
to Power-Supply Noise
(Note 8)
DJ
PN,P-P
1MHz 7.0
ps
Rise and Fall Time
Mismatching
20% to 80%; CL = 2pF; Figure 2;
2 x (t
R
- t
F
) / (t
R
+ t
F
)
±20 %
Duty Cycle t
DC
Measure at OUTP and OUTN, Figure 2 45 55 %
Oscillation Startup Time (Note 9) 3 ms
100Hz -90.0
1kHz -112
10kHz -115
100kHz -123
1MHz -142
Clock Output SSB
Phase Noise
10MHz -147
dBc/
Hz