Datasheet

Figure 1. DS3923 Sample/Hold Timing Diagram
GAIN VALID
SENINT
VIP1/VIP2
VOLTAGE INVALIDVOP - VON
EXTERNAL
ADC DATA
t
ADC
DATA VALID
GAIN GAIN VALID
t
S
= SAMPLE TIME t
DEL
= DELAY TIME t
O_VAL
= OUTPUT VALID TIME
VIP1 < 0.4
VIP1 > = 0.4
UPPER LIMIT (UL)
(0.91 x 4 x IM x R
VIP1
)/1.25 (1.09 x 4 x IM x R
VIP1
)/1.25
LOWER LIMIT (LL)
(0.91 x 4 x IM x R
VIP2
)/5 (1.09 x 4 x IM x R
VIP2
)/5
VOP - VON
IM = MIRROR CURRENT
R
VIP1
: RESISTOR BETWEEN VIP1 TO GROUND
R
VIP2
: RESISTOR BETWEEN VIP2 TO GROUND
UL
LL
t
ADC
= ADC CONVERSION TIME
t
DEL
t
S
OUTPUT VALID
t
O_VAL MAX
t
O_VAL
MIN
DS3923 High-Speed Current Mirror
with Sample/Hold Output
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