Datasheet

Applications Information
Layout Considerations
Proper PCB layout helps to reduce switching noise in the
system. HVGND is the connection of the switching FET
and thus carries high current pulses. HVGND should also
be connected to the boost converter’s input capacitor and
output bulk capacitor. Ensure that the HVGND trace is
low impedance and able to carry the high current from
the FET. To keep the switching noise on HVGND isolated
from GND, a star ground configuration should be used.
HVGND and GND should only be connected together at
one point on the PCB. This point can be either the ground
side of the output bulk capacitor or the common ground
point of the PCB. Keeping all PCB traces as short as
possible reduces radiated noise, stray capacitance, and
trace resistance.
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
24 TQFN-EP T243A3+1 21-0188 90-0122
Ordering Information
PART TEMP TANGE PIN-PACKAGE
DS3923T+ -40°C to +95°C 24-TQFN-EP**
DS3923T+T* -40°C to +95°C 24-TQFN-EP**
+Denotes a lead(Pb)-free/RoHS-compliant package.
*First T denotes package type. Second T denotes Tape and reel.
**EP = Exposed pad.
Figure 6. GAIN Selection Logic Diagram
COMPARATOR
DS3923
400mV
VIP1
VIP2
SENINT
NOT
R
G
GAIN
SAMPLE/HOLD
AMPLIFIER
X4
VOP
VON
NOT
Q
D
DS3923 High-Speed Current Mirror
with Sample/Hold Output
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Maxim Integrated │ 14
Chip Information
PROCESS: BiCMOS