Datasheet

Alternatively, forcing GAIN = 0 always chooses VIP1 and
forcing GAIN = V
CC
chooses VIP2. By default, GAIN pin
is pulled high.
The logical circuit is shown in Figure 6.
Output Buffer
After sampling is complete, the sampling capacitor is
switched to the output buffer. This buffer requires a
small amount of time to settle, t
OUT
(see the Electrical
Characteristics table) as shown in Figure 3. When an ADC
is used to measure the DS3923’s output, a step will occur
at the ADC’s input caused by its sampling capacitor. The
DS3923’s t
REC
is dependent on the size of this sampling
capacitor and the voltage applied across it. To maximize
accuracy, the ADC’s sampling speed (ADC clock frequen-
cy) should be slowed down until the ADC’s acquisition
window is larger than the DS3923’s recovery time.
Sampling Time and Output Error
As sampling time (t
S
) decreases, V
ERR
increases. V
ERR
is largely dependent on the settling time of the sampling
capacitor, and to a lesser degree to the buffer’s gain error
and offset voltage. Settling time can be reduced by reduc-
ing the resistor connected between the sample/hold ampli-
fier’s input and ground. However, a smaller resistor will
decrease the amplitude of the sampled signal, and cause
the relative offset errors to become more significant.
High-Voltage (HV) Switch FET
A high-voltage (HV) switching FET is included to option-
ally be used in a DC-DC converter in order to supply the
APD bias voltage. APD biasing of 15V to 76V can be
achieved using the DS3923.
Table 2. Sample/Hold Input Selection
VIP1 INPUT SELECTED OUTPUT VOLTAGE GAIN OUTPUT
< 0.4V VIP1 4 × VIP1 0
≥ 0.4V VIP2 4 × VIP2 V
CC
Figure 5. Discharge, Current Mirror, and SEN Pulse Timing Diagram
DISCHARGE ENABLE
t
S
t
S
SEN PULSE
SEN PULSE
DISCHARGE DISABLE
VIP1
VIP2
VIP1
VIP2
DS3923 High-Speed Current Mirror
with Sample/Hold Output
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