Datasheet

In addition to VIP1 or VIP2 auto selection, the DS3923
allows VIP1 or VIP2 forced selection using the GAIN pin.
The sample/hold amplifier output is shown in Table 1.
Sampling Capacitors
Each sample/hold input voltage is sampled using an
internal capacitor. As shown in the Block Diagram, when
SENXOR is low, the capacitors are connected to the input
during the high time of the SEN pulse. When SENXOR is
high, the capacitors are connected to the input during the
low time of the SEN pulse. These capacitors must be fully
charged before SEN becomes inactive in order to ensure
accurate sampling. An RC time constant is created by the
resistance of the voltage source connected to the sample/
hold’s input and the DS3923’s sampling capacitors. An
external capacitor may be used on the sample/hold’s
inputs. This external capacitance will be in parallel with
the pin’s ESD capacitance (~7pF). These capacitors can
be discharged when the DS3923 is not sampling the input
by setting the DISCHARGE pin to high.
Discharge
When the DISCHARGE pin is set to logic-high, the
DS3923 pulls down current mirror outputs VIP1 and VIP2
to low. The discharge strength is about 50Ω. During the
sample time t
S
, the pin discharge is internally disabled
by the DS3923 as shown in Figure 4 and Figure 5. When
the DISCHARGE pin is set to logic-low, the pin discharge
function is disabled.
Note: The discharge function should not be used if
SENXOR is a logic high.
Gain Selection
The sample/hold circuit has a native gain of 4 applied to
the input presented. Depending on the level of VIP1, a
selection is made to present either VIP1 or VIP2 to the
sample/hold circuit when SEN pulse is applied. The sam-
ple circuit applied to this buffer is chosen by a reference
voltage (400mV) and a comparator to avoid outputing a
clipped value. Table 2 lists the conditions that make the
choice. The choice made is indicated on the GAIN pin.
Table 1. Sample/Hold Output Voltage
vs. Input
INPUT SELECTED
(AUTO OR FORCED)
SAMPLE/HOLD
OUTPUT VOLTAGE
VIP1
4 VIP1 4 0.8 I1 R4
3 . 2 I1 R 4
× =× ××
= ××
VIP2
4 VIP2 4 0.2 I1 R5
0 . 8 I1 R5
× =× ××
= ××
Figure 4. Discharge Logic Diagram
XOR
NOR
SEN
SENXOR
PIN DISCHARGE
INACTIVE
DURING SEN PULSE
SENINT
PIN
DISCHARGE
DS3923
NOT
VIP1
VIP2
VIN
~50Ω
FETs
SENXOR SAMPLE PULSE
LOW
HIGH
RISING EDGE
FALLING EDGE
DS3923 High-Speed Current Mirror
with Sample/Hold Output
www.maximintegrated.com
Maxim Integrated │ 12